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dirname:
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filenames: altera_10gbaser_phy_clockcomp.sv/altera_10gbaser_phy_rx_fifo.sv/altera_10gbaser_phy_soft_fifo.v
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dirname:
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dirname:
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filenames:
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filetypes: ffffffffffff
dirname:
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filenames:
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filenames: msa_ddr4_fm.sdc
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dirname:
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filetypes: fffff
dirname:
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filenames:
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dirname: /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/ethernet/tse_ucores
filetypes: ddddddddddddddddddddddd
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filenames: alt_e40_sys_pll_sv_100_0002.qip/alt_e40_sys_pll_sv_100_0002.v
filetypes: ff
dirname:
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filetypes: ffffff
dirname:
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filenames:
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filetypes: fffffffffffffffffffffffffff
dirname:
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filenames:
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filenames: dec/enc
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dirname:
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filenames: altera_rs_ser_correct.sv
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filenames: src_hdl
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dirname:
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filenames: alt_e40_block_distributor.v/alt_e40_pcs.v/alt_e40_pcs_rx.v/alt_e40_pcs_tx.v
filetypes: ffff
dirname:
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filetypes: fffffffffff
dirname:
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filenames:
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filetypes: fffffffffffffffffffffffffffffffffff
dirname:
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filenames:
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filenames: common/hwtest/templates
filetypes: ddd
dirname:
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filenames: src_hdl
filetypes: d
dirname:
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filetypes: ffffffffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/ethernet/alt_em10g32/example_design/LL10G_1G_2_5G/rtl/ethernet_traffic_controller/eth_1588_traffic_controller/TrafficController_1588_10g

filenames:
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