# filelist

filenames: source
filetypes: d
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/alt_xcvr/altera_xcvr_pll/altera_xcvr_fpll_vi/mentor


filenames: cons/operators/requirements
filetypes: ddd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/nios2eds/bin/gnu/src/gcc-8.3.1/libstdc++-v3/testsuite/ext/random/von_mises_distribution


filetypes: ffffffffffffdddfdddffddfddfddf
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/nios2eds/bin/gnu/src/gcc-8.3.1/libstdc++-v3/testsuite/23_containers/vector

filenames:
  14340.cc/15523.cc/18604.cc/26412-1.cc/26412-2.cc/40192.cc/48101-2_neg.cc/48101_neg.cc/52591.cc/58764.cc/59829.cc/63500.cc/allocator/bool/capacity/check_construct_destroy.cc/cons/data_access/debug/debug_mode_requires_reallocation-1.cc/debug_mode_requires_reallocation-2.cc/element_access/ext_pointer/init-list.cc/modifiers/profile/range_access.cc/requirements/types/zero_sized_allocations.cc


filenames: requirements/value.cc
filetypes: df
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/nios2eds/bin/gnu/src/gcc-8.3.1/libstdc++-v3/testsuite/20_util/is_class


filenames: 1.cc/18654.cc/2.cc/shrink_to_fit.cc
filetypes: ffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/nios2eds/bin/gnu/src/gcc-8.3.1/libstdc++-v3/testsuite/21_strings/basic_string/capacity/char


filenames: 1.cc/2.cc/3.cc/4.cc/5.cc/6.cc
filetypes: ffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/nios2eds/bin/gnu/src/gcc-8.3.1/libstdc++-v3/testsuite/experimental/optional/relops


filetypes: ffffffffffffffffffffffffffffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/dsp/altera_highspeed_rs/src/reference_designs/25_100g_ethernet/dec/synopsys

filenames:
  rsp_fifo.vhd/rsp_gf_add.vhd/rsp_gf_mr.vhd/rsp_gf_mul.vhd/rsp_gf_mulx.vhd/rsp_gf_pp.vhd/rsp_unary.vhd/rsx_bm_auto.vhd/rsx_bm_offset.vhd/rsx_bm_pe1.vhd/rsx_bm_pe2.vhd/rsx_bm_pe4.vhd/rsx_bm_pe6.vhd/rsx_count_errors.vhd/rsx_decoder.vhd/rsx_error_dot.vhd/rsx_fit_counter.vhd/rsx_functions.vhd/rsx_gf_inv.vhd/rsx_inverse_ROM_auto.vhd/rsx_inverse_ROM_bkp.vhd/rsx_omega_pipe.vhd/rsx_omega_vecpipe.vhd/rsx_package.vhd/rsx_parameters_auto.vhd/rsx_poly_dot.vhd/rsx_roots_auto.vhd/rsx_search.vhd/rsx_searches.vhd/rsx_searcheslast.vhd/rsx_syndrome.vhd/rsx_syndrome_fifo.vhd/rsx_syndrome_poly.vhd/rsx_syndrome_zero.vhd


filetypes: fffffdffdff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/dynamic_reconfiguration/etile_dynamic_reconfiguration/example_design/ETH25G_RSFEC/hardware_test_design

filenames:
  alt_ehipc3.qpf/alt_ehipc3.qsf.terp/alt_ehipc3.sdc/alt_ehipc3.sv/alt_ehipc3_devkit.qsf.terp/common/eth_25g_channel_pll_s10.ip/ex_25G_s10.ip/ip_s10/nios_system_s10.qsys/reset_release_s10.ip


filenames: top_hw.v
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/altera_pcie/altera_pcie_sriov/mentor/hw_devkit


filenames: typedefs.cc
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/nios2eds/bin/gnu/src/gcc-8.3.1/libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/requirements


filenames: src
filetypes: d
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/dsp/altera_bch/mentor/bch_dec


dirname: /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/emif/ip_ctrl/ip_rld3
filetypes: ffffffffffd
filenames:
  altera_emif_ctrl_rld3_hw.tcl/common_gui.properties/common_messages.properties/common_params.properties/common_ports.properties/ctrl_expert_exports.tcl/enum_defs.tcl/gui.properties/main.tcl/messages.properties/rtl


filetypes: ffffffffffffffffffffffffffffffffffffffffffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/altera_10gbaser_phy/soft_pcs/cadence

filenames:
  alt_10gbaser_pcs.v/altera_10gbaser_phy_1588_latency.sv/altera_10gbaser_phy_async_fifo.sv/altera_10gbaser_phy_async_fifo_fpga.sv/altera_10gbaser_phy_ber.v/altera_10gbaser_phy_ber_cnt_ns.v/altera_10gbaser_phy_ber_sm.v/altera_10gbaser_phy_bitsync.v/altera_10gbaser_phy_blksync.v/altera_10gbaser_phy_blksync_datapath.v/altera_10gbaser_phy_clk_ctrl.v/altera_10gbaser_phy_clock_crosser.v/altera_10gbaser_phy_clockcomp.sv/altera_10gbaser_phy_decode.sv/altera_10gbaser_phy_decode_type.sv/altera_10gbaser_phy_descramble.v/altera_10gbaser_phy_encode.sv/altera_10gbaser_phy_encode_type.sv/altera_10gbaser_phy_gearbox_exp.v/altera_10gbaser_phy_gearbox_red.v/altera_10gbaser_phy_lock_sm.v/altera_10gbaser_phy_nto1mux.v/altera_10gbaser_phy_params.sv/altera_10gbaser_phy_pcs_10g.v/altera_10gbaser_phy_pcs_10g_top.sv/altera_10gbaser_phy_pipeline_base.v/altera_10gbaser_phy_pipeline_stage.sv/altera_10gbaser_phy_prbs_gen_xg.v/altera_10gbaser_phy_prbs_ver_xg.v/altera_10gbaser_phy_random_err_cnt_ns.sv/altera_10gbaser_phy_random_gen.sv/altera_10gbaser_phy_random_ver.sv/altera_10gbaser_phy_random_ver_10g.sv/altera_10gbaser_phy_reg_map_av.sv/altera_10gbaser_phy_register_with_byte_enable.v/altera_10gbaser_phy_rx_fifo.v/altera_10gbaser_phy_rx_fifo_wrap.v/altera_10gbaser_phy_rx_sm_datapath.sv/altera_10gbaser_phy_rx_sm_ns.sv/altera_10gbaser_phy_rx_top.v/altera_10gbaser_phy_scramble.v/altera_10gbaser_phy_square_wave_gen.v/altera_10gbaser_phy_tx_sm_datapath.sv/altera_10gbaser_phy_tx_sm_ns.sv/altera_10gbaser_phy_tx_top.v/altera_10gbaser_phy_word_align.v/gearbox_exp.v/nto1mux.v


filetypes: fffffffffffffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/nios2eds/bin/gnu/src/gcc-8.3.1/libstdc++-v3/include/c_std

filenames:
  cassert/cctype/cerrno/cfloat/ciso646/climits/clocale/cmath/csetjmp/csignal/cstdarg/cstddef/cstdio/cstdlib/cstring/ctime/cuchar/cwchar/cwctype


filenames: opt_random.h
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/nios2eds/bin/gnu/nios2-elf/include/c++/8.3.1/nios2-elf/march-r2/mbmx/mcdx/fstack-limit-register-et/pg/ext


filenames: altera_eth_pause_req_termination_hw.tcl
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/ethernet/ethernet_ucore/altera_eth_adapters/altera_eth_pause_req_termination


filetypes: ffffffffffffffffffffffffffffffffffffffffffffffffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/quartus/linux64/qt/qml/QtQuick/Controls.2/Fusion

filenames:
  ApplicationWindow.qml/BusyIndicator.qml/Button.qml/ButtonPanel.qml/CheckBox.qml/CheckDelegate.qml/CheckIndicator.qml/ComboBox.qml/DelayButton.qml/Dial.qml/Dialog.qml/DialogButtonBox.qml/Drawer.qml/Frame.qml/GroupBox.qml/ItemDelegate.qml/Label.qml/Menu.qml/MenuBar.qml/MenuBarItem.qml/MenuItem.qml/MenuSeparator.qml/Page.qml/PageIndicator.qml/Pane.qml/Popup.qml/ProgressBar.qml/RadioButton.qml/RadioDelegate.qml/RadioIndicator.qml/RangeSlider.qml/RoundButton.qml/ScrollBar.qml/ScrollIndicator.qml/ScrollView.qml/Slider.qml/SliderGroove.qml/SliderHandle.qml/SpinBox.qml/SwipeDelegate.qml/Switch.qml/SwitchDelegate.qml/SwitchIndicator.qml/TabBar.qml/TabButton.qml/TextArea.qml/TextField.qml/ToolBar.qml/ToolButton.qml/ToolSeparator.qml/ToolTip.qml/Tumbler.qml/libqtquickcontrols2fusionstyleplugin.so/qmldir


filenames: altera_avalon_jtag_uart_lwhal.h
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/LWHAL/inc


filenames: intel_generic_serial_flash_interface_addr.sv/intel_generic_serial_flash_interface_addr_hw.tcl
filetypes: ff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/pgm/intel_generic_serial_flash_interface/intel_generic_serial_flash_interface_addr


filenames: Y.pl
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/quartus/linux64/perl/lib/5.28.1/unicore/lib/CI


filenames: opt_random.h
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/nios2eds/bin/gnu/nios2-elf/include/c++/8.3.1/nios2-elf/march-r2/mhw-mulx/ext


filenames: alt_e100_phy_pcs.v/alt_e100_phy_pcs_caui4.v/common/rx/tx
filetypes: ffddd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/alt_eth_40g_100g/100gbe/rtl_src/phy/cadence/pcs


filenames: altera_up_avalon_ps2.h/altera_up_avalon_ps2_regs.h/altera_up_ps2_keyboard.h/altera_up_ps2_mouse.h
filetypes: ffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/university_program/input_output/altera_up_avalon_ps2/HAL/inc


filenames: alt_aeu_100_pfc_top.v
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/ethernet/alt_eth_ultra/100g/synopsys/rtl/pfc/top


filenames: alt_ntrlkn_gxb_reset.v/alt_ntrlkn_reset.v/alt_ntrlkn_reset_delay.v/alt_ntrlkn_reset_hw.tcl
filetypes: ffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/alt_interlaken/alt_interlaken_rst


filenames: char/wchar_t
filetypes: dd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/nios2eds/bin/gnu/src/gcc-8.3.1/libstdc++-v3/testsuite/21_strings/basic_string/operations/substr


filenames: 1.cc
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/nios2eds/bin/gnu/src/gcc-8.3.1/libstdc++-v3/testsuite/experimental/string_view/operations/copy/wchar_t


filenames: altera_eth_tse_pcs_pma_nf_phyip.v
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/ethernet/tse_ucores/altera_eth_tse_pcs_pma_nf_phyip/cadence


filenames: node_metadata_selector.hpp/order_statistics_imp.hpp/sample_tree_node_update.hpp
filetypes: fff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/nios2eds/bin/gnu/nios2-elf/include/c++/8.3.1/ext/pb_ds/detail/tree_policy


filenames: src_hdl
filetypes: d
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/vip/ip_library/common_hdl/cadence/modules/alt_vip_common_video_packet_decode


filenames: alt_mem_if_lpddr_mem_model.qprs/alt_mem_if_lpddr_tg_ed_hw.tcl
filetypes: ff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/alt_mem_if/alt_mem_if_example_designs/alt_mem_if_lpddr_tg_ed


filenames: altera_mailbox_urg_controller.sv/altera_mailbox_urg_controller_hw.tcl
filetypes: ff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/pgm/altera_nd_mailbox_driver/altera_mailbox_urgent_controller


filenames: aldec/alt_vip_guard_bands_scheduler_hw.tcl/cadence/mentor/src_hdl/synopsys
filetypes: dfdddd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/vip/ip_library/component_ip/schedulers/alt_vip_guard_bands_scheduler


filenames: kr
filetypes: d
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/ethernet/alt_ehipc3/mentor/rtl


filenames: char/wchar_t
filetypes: dd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/nios2eds/bin/gnu/src/gcc-8.3.1/libstdc++-v3/testsuite/21_strings/basic_string/numeric_conversions


filenames: 1.cc/9425.cc
filetypes: ff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/nios2eds/bin/gnu/src/gcc-8.3.1/libstdc++-v3/testsuite/27_io/basic_stringbuf/sputbackc/wchar_t


filenames: altera_avalon_st_sink_bfm_vhdl.vhd/altera_avalon_st_sink_bfm_vhdl_pkg.vhd
filetypes: ff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/sopc_builder_ip/verification/altera_avalon_st_sink_bfm_vhdl


filenames: gprof.mo/ld.mo/opcodes.mo
filetypes: fff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/nios2eds/bin/gnu/share/locale/pt_BR/LC_MESSAGES


filetypes: fff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/sld/mm/altera_mm_debug_link

filenames:
  altera_mm_debug_link_addr_fixer_hw.tcl/altera_mm_debug_link_constant_hw.tcl/altera_mm_debug_link_hw.tcl


filenames: mpf_handle.cpp/mpf_shared_buffer.cpp
filetypes: ff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/board/intel_s10sx_pac/hardware/pac_s10_usm/build/BBB_cci_mpf/sw/src/libmpf++


filenames: hwtest/rtl/simulation
filetypes: ddd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/sdi_ii/sdi_ii_example_design/common


filenames: alt_vip_cpp_converter.sv
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/vip/ip_library/component_ip/utility/alt_vip_cpp_converter/aldec/src_hdl


filetypes: ffffffffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/ethernet/alt_em10g32/example_design/LL10G_1G_2_5G_1588v2/rtl/altera_eth_1588_tod

filenames:
  alt_mge_1588_tod_1g_a10.qsys/alt_mge_1588_tod_1g_s10.ip/alt_mge_1588_tod_2p5g_a10.qsys/alt_mge_1588_tod_2p5g_s10.ip/alt_mge_1588_tod_master_a10.qsys/alt_mge_1588_tod_master_s10.ip/alt_mge_1588_tod_sync_64b_1g_a10.qsys/alt_mge_1588_tod_sync_64b_1g_s10.ip/alt_mge_1588_tod_sync_64b_2p5g_a10.qsys/alt_mge_1588_tod_sync_64b_2p5g_s10.ip/alt_mge_1588_tod_sync_96b_1g_a10.qsys/alt_mge_1588_tod_sync_96b_1g_s10.ip/alt_mge_1588_tod_sync_96b_2p5g_a10.qsys/alt_mge_1588_tod_sync_96b_2p5g_s10.ip


filetypes: fddffffffffffffdddd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/nios2-elf/lib

filenames:
  crt0.o/fstack-limit-register-et/ldscripts/libc.a/libg.a/libm.a/libnosys.a/libsmallc.a/libsmallg.a/libstack.a/libstdc++.a/libstdc++.a-gdb.py/libstdc++.la/libsupc++.a/libsupc++.la/march-r2/mhw-mulx/mno-hw-mul/pg


filenames: altera_mem_if_qdrii_qseq_hw.tcl
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/alt_mem_if/altera_mem_if_qseq/altera_mem_if_qdrii_qseq


filetypes: ffffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/ethernet/alt_eth_ultra/40g_kr4_a10/mentor/reconfig

filenames:
  alt_aeu_40_rcfg_avmm_mstr.sv/alt_aeu_40_rcfg_ctle_ctrl.sv/alt_aeu_40_rcfg_data_322.sv/alt_aeu_40_rcfg_data_644.sv/alt_aeu_40_rcfg_data_fec_322.sv/alt_aeu_40_rcfg_data_fec_644.sv/alt_aeu_40_rcfg_dfe_ctrl.sv/alt_aeu_40_rcfg_pcs_ctrl.sv/alt_aeu_40_rcfg_top.sv/alt_aeu_40_rcfg_txeq_ctrl.sv


dirname: /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/board/intel_s10sx_pac/hardware/pac_s10_usm/build/ip/board
filetypes: fffffffffffffffffffffffffff
filenames:
  board_acl_avalon_mm_bridge_s10_0.ip/board_acl_avalon_mm_bridge_s10_1.ip/board_acl_avalon_mm_bridge_s10_2.ip/board_acl_avalon_mm_bridge_s10_3.ip/board_acl_avalon_mm_bridge_s10_4.ip/board_acl_avalon_mm_bridge_s10_5.ip/board_acl_avalon_mm_bridge_s10_6.ip/board_acl_hyper_optimized_ccb_0.ip/board_acl_hyper_optimized_ccb_1.ip/board_afu_id_avmm_slave_0.ip/board_clk_200.ip/board_clock_bridge_0.ip/board_clock_bridge_1.ip/board_global_reset_in.ip/board_irq_ctrl_0.ip/board_kernel_clk_export.ip/board_kernel_clk_in.ip/board_kernel_cra_clockcross.ip/board_kernel_cra_reset.ip/board_kernel_interface.ip/board_kernel_interface_s10_0.ip/board_pipe_stage_host_ctrl.ip/emif_ddr4a_clk_0.ip/emif_ddr4b_clk_0.ip/kernel_mm_bridge_burst16.ip/kernel_mm_bridge_burst4.ip/kernel_mm_bridge_burst8.ip


filetypes: ffdfffdfdf
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/altera_dp/de_gen/cyclone_10/rtl

filenames:
  bitec_reconfig_alt_c10.v/c10_reconfig_arbiter.sv/core/example.sdc/reset_gen.sv/reset_sync.sv/rx_phy/top.v.terp/tx_phy/video_pll_c10.tcl.terp


filetypes: ffffffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/ethernet/alt_eth_ultra/40g_kr4_a10/cpu

filenames:
  kr4a10_cpu_dmem.hex/kr4a10_cpu_dmem_es.hex/kr4a10_cpu_gen2_hw.tcl/kr4a10_cpu_hw.tcl/kr4a10_cpu_imem.hex/kr4a10_cpu_imem_es.hex/kr4a10_debug_cpu_dmem.hex/kr4a10_debug_cpu_dmem_es.hex/kr4a10_debug_cpu_gen2_hw.tcl/kr4a10_debug_cpu_hw.tcl/kr4a10_debug_cpu_imem.hex/kr4a10_debug_cpu_imem_es.hex


filenames: constructible.cc/explicit_instantiation/typedefs.cc/uses_allocator.cc
filetypes: fdff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/nios2eds/bin/gnu/src/gcc-8.3.1/libstdc++-v3/testsuite/23_containers/priority_queue/requirements


filetypes: fff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/vip/ip_library/component_ip/processing/alt_vip_tpg_bars_alg_core/cadence/src_hdl

filenames:
  alt_vip_tpg_bars_alg_core.sv/alt_vip_tpg_bars_alg_core_par_lut.sv/alt_vip_tpg_bars_alg_core_seq_lut.sv


filetypes: fffff
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lt_e2550_frame_256to511b.v/alt_e2550_frame_512to1023b.v/alt_e2550_frame_64b.v/alt_e2550_frame_65to127b.v/alt_e2550_frmwatch.v/alt_e2550_gte_with_const_16b.v/alt_e2550_hw_reg.v/alt_e2550_ilv66.v/alt_e2550_inpkt1t1.v/alt_e2550_inpkt2t1.v/alt_e2550_locklag10.v/alt_e2550_locklag5.v/alt_e2550_lte.v/alt_e2550_lte_with_const_16b.v/alt_e2550_lut6.v/alt_e2550_metronome1280.v/alt_e2550_metronome32000.v/alt_e2550_metronome320000.v/alt_e2550_metronome32768.v/alt_e2550_metronome512.v/alt_e2550_metronome81920.v/alt_e2550_mlab.sv/alt_e2550_mlab11a3r1w1.v/alt_e2550_mlab16a1r1w1.v/alt_e2550_mlab20a5r0w0.v/alt_e2550_mlab20a5r1w1e.v/alt_e2550_mlab2a5r1w1.v/alt_e2550_mlab32a4r1w1.v/alt_e2550_mlab34a2r1w1.v/alt_e2550_mlab44a2r1w1.v/alt_e2550_mlab44a3r1w1.v/alt_e2550_mlab4a4r1w1.v/alt_e2550_mlab5a4r1w1.v/alt_e2550_mlab64a2r1w1.v/alt_e2550_mlab64a3r1w1.v/alt_e2550_mlab64a4r1w1.v/alt_e2550_mlab64a5r1w1.v/alt_e2550_mlab69a5r1w1.v/alt_e2550_mlab6a3r1w1.v/alt_e2550_mlab8a4r1w1.v/alt_e2550_mlab_32word_32bit.v/alt_e2550_mlcume1.v/alt_e2550_mlcume10.v/alt_e2550_mlstat32i1c10o64.v/alt_e2550_mlstat32i2c10o64.v/alt_e2550_mlstsh64.v/alt_e2550_mtywipe.v/alt_e2550_mtywipe_comb.v/alt_e2550_mux16w10t2s1.v/alt_e2550_mux16w1t1s0.v/alt_e2550_mux2w10t0s0.v/alt_e2550_mux2w10t0s1.v/alt_e2550_mux2w10t0s2.v/alt_e2550_mux2w10t0s3.v/alt_e2550_mux2w10t1s3.v/alt_e2550_mux2w1t0s0.v/alt_e2550_mux2w1t0s1.v/alt_e2550_mux2w1t0s2.v/alt_e2550_mux2w1t1s1.v/alt_e2550_mux2w1t1s2.v/alt_e2550_mux2w2t0s0.v/alt_e2550_mux2w2t0s1.v/alt_e2550_mux2w2t1s1.v/alt_e2550_mux2w32t0s0.v/alt_e2550_mux2w32t0s1.v/alt_e2550_mux2w32t0s2.v/alt_e2550_mux2w32t1s2.v/alt_e2550_mux2w33t0s0.v/alt_e2550_mux2w33t0s1.v/alt_e2550_mux2w33t1s1.v/alt_e2550_mux2w40t0s0.v/alt_e2550_mux2w40t0s1.v/alt_e2550_mux2w40t1s1.v/alt_e2550_mux2w56t0s0.v/alt_e2550_mux2w56t1s0.v/alt_e2550_mux2w5t0s0.v/alt_e2550_mux2w5t0s1.v/alt_e2550_mux2w5t1s1.v/alt_e2550_mux2w66t0s0.v/alt_e2550_mux2w66t0s1.v/alt_e2550_mux2w66t1s1.v/alt_e2550_mux2w7t0s0.v/alt_e2550_mux2w7t0s1.v/alt_e2550_mux2w7t1s1.v/alt_e2550_mux2w8t0s0.v/alt_e2550_mux2w8t1s0.v/alt_e2550_mux2w8t2s0.v/alt_e2550_mux2w9t0s0.v/alt_e2550_mux2w9t0s1.v/alt_e2550_mux2w9t1s1.v/alt_e2550_mux32w10t3s1.v/alt_e2550_mux3w1t0s0.v/alt_e2550_mux3w1t0s1.v/alt_e2550_mux3w1t1s1.v/alt_e2550_mux4w10t0s0.v/alt_e2550_mux4w10t0s1.v/alt_e2550_mux4w10t0s2.v/alt_e2550_mux4w10t1s1.v/alt_e2550_mux4w10t1s2.v/alt_e2550_mux4w1t0s0.v/alt_e2550_mux4w1t0s1.v/alt_e2550_mux4w1t1s1.v/alt_e2550_mux4w33t0s0.v/alt_e2550_mux4w33t0s1.v/alt_e2550_mux4w33t1s1.v/alt_e2550_mux4w36t0s0.v/alt_e2550_mux4w36t0s1.v/alt_e2550_mux4w36t1s1.v/alt_e2550_mux4w3t0s0.v/alt_e2550_mux4w3t0s1.v/alt_e2550_mux4w3t1s1.v/alt_e2550_mux4w66t0s0.v/alt_e2550_mux4w66t0s1.v/alt_e2550_mux4w66t1s1.v/alt_e2550_mux4w8t0s0.v/alt_e2550_mux4w8t1s0.v/alt_e2550_mux4w8t2s0.v/alt_e2550_mux4w96t0s0.v/alt_e2550_mux4w96t0s1.v/alt_e2550_mux4w96t1s1.v/alt_e2550_mux4w9t0s0.v/alt_e2550_mux4w9t1s0.v/alt_e2550_mux66w1t2s0.v/alt_e2550_mux8w1t2s1.v/alt_e2550_mux8w9t2s0.v/alt_e2550_mx16r.v/alt_e2550_mx4r.v/alt_e2550_neq_5_ena.v/alt_e2550_octets_ok.v/alt_e2550_ohbin4.v/alt_e2550_ohbin8.v/alt_e2550_opp2t0.v/alt_e2550_opp2t1.v/alt_e2550_opp32t3.v/alt_e2550_opp33t3.v/alt_e2550_opp3t0.v/alt_e2550_opp3t1.v/alt_e2550_or16t2.v/alt_e2550_or1t0.v/alt_e2550_or1t1.v/alt_e2550_or1t2.v/alt_e2550_or2t0.v/alt_e2550_or2t1.v/alt_e2550_or2t2.v/alt_e2550_or4t0.v/alt_e2550_or4t1.v/alt_e2550_or8t2.v/alt_e2550_or_r.sv/alt_e2550_perminv4.v/alt_e2550_pipeline_adder_16b.v/alt_e2550_pll_recal.sv/alt_e2550_pllmon.v/alt_e2550_ptp_altsyncram.v/alt_e2550_ptp_altsyncram_bundle.v/alt_e2550_ptp_async_fifo.sv/alt_e2550_ptp_bitslip.sv/alt_e2550_ptp_clock_crosser.v/alt_e2550_ptp_fifo_latency.sv/alt_e2550_ptp_fifo_top.sv/alt_e2550_ptp_pipeline_base.v/alt_e2550_ptp_rx_fifo.sv/alt_e2550_ptp_sc_fifo.v/alt_e2550_ptp_tx_fifo.sv/alt_e2550_pulse16.v/alt_e2550_pulse2.v/alt_e2550_pulse4.v/alt_e2550_pulse64.v/alt_e2550_pulse8.v/alt_e2550_pulse_stretcher.v/alt_e2550_pulse_transfer.v/alt_e2550_readmii1.v/alt_e2550_readmii2.v/alt_e2550_ready_skid.v/alt_e2550_ripple16.v/alt_e2550_rxmon.v/alt_e2550_scfifo_mlab.v/alt_e2550_scram128.v/alt_e2550_scram64.v/alt_e2550_secwa66.v/alt_e2550_shr88s3h8.v/alt_e2550_stat64c32i1.v/alt_e2550_stat64c32i2.v/alt_e2550_stat_ram_16x64b.v/alt_e2550_stat_ram_32x32b.v/alt_e2550_stats_counters.v/alt_e2550_subc2h0t1.v/alt_e2550_subc2h1t1.v/alt_e2550_subc2h2t1.v/alt_e2550_subc3h3t1.v/alt_e2550_subc3h4t1.v/alt_e2550_subc3h5t1.v/alt_e2550_subc3h6t1.v/alt_e2550_subc4h7t1.v/alt_e2550_subc4hat1.v/alt_e2550_subc4hbt1.v/alt_e2550_subc4hct1.v/alt_e2550_subc4hdt1.v/alt_e2550_subc5h01t1.v/alt_e2550_subc5h0ft1.v/alt_e2550_subc5h10t1.v/alt_e2550_sv.v/alt_e2550_swap132.v/alt_e2550_swap66.v/alt_e2550_sync16m.v/alt_e2550_sync1r1.v/alt_e2550_sync1r2.v/alt_e2550_sync1r3.v/alt_e2550_sync2r2.v/alt_e2550_sync_read.v/alt_e2550_sync_regs_m2.v/alt_e2550_synchronizer.v/alt_e2550_twodel69.v/alt_e2550_tx_fc_arbiter_ctrl.v/alt_e2550_tx_fc_ctrl.v/alt_e2550_tx_fc_onoff_ctrl.v/alt_e2550_tx_fc_pb_conv.v/alt_e2550_tx_fc_pb_timer.v/alt_e2550_txmon.v/alt_e2550_watchdog16.v/alt_e2550_wdly33.v/alt_e2550_wys_lut.v/alt_e2550_xor1t0.v/alt_e2550_xor1t1.v/alt_e2550_xor2t0.v/alt_e2550_xor2t1.v/alt_e2550_xor3t0.v/alt_e2550_xor3t1.v/alt_e2550_xor4t0.v/alt_e2550_xor4t1.v/alt_e2550_xor5t0.v/alt_e2550_xor5t1.v/alt_e2550_xor6t0.v/alt_e2550_xor6t1.v/alt_e2550_xrise1r3.v/alt_e25s10_etag.v/alt_e25s10_ethdec.v/alt_e25s10_ethenc.v/alt_e25s10_frmwatch.v/alt_e25s10_rxmon.v/alt_e25s10_txmon.v/latency_pulse_measurement.v/latency_pulse_measurement_top.v

filetypes:
  ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff


filetypes: ffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/quartus/common/devkits/odyssey_max_10_fpga_kit

filenames:
  Odyseey_MAX 10_board_tilted.jpg/odyssey_block_diagram.jpg/odyssey_board.png/odyssey_max_10_fpga_kit.devkit_info


filenames: Queue.pm/Semaphore.pm
filetypes: ff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/quartus/linux64/perl/lib/5.28.1/Thread


filenames: cons/operators/requirements
filetypes: ddd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/nios2eds/bin/gnu/src/gcc-8.3.1/libstdc++-v3/testsuite/26_numerics/random/uniform_real_distribution


filenames: alt_vip_cl_clp_hw.tcl/alt_vip_cl_clp_sw.tcl
filetypes: ff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/vip/ip_library/full_ip/alt_vip_cl_clp


filetypes: ffffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/altera_pcie/altera_pcie_hip_ast_tbed/verilog/tbsysver

filenames:
  altpcietb_bfm_ast_monitor.sv/altpcietb_bfm_driver_rp.sv/altpcietb_bfm_rp_gen3_x8.v/altpcietb_bfm_vc_intf_ast.sv/altpcietb_bfm_vc_intf_mon.sv/altpcietb_bfm_vc_intf_param.sv/altpcietb_bfm_vc_intf_param_pkg.sv/altpcietb_bfm_vc_intf_tlp_process.sv/altpcietb_bfm_vc_intf_tx_driver.sv/avmmdma_rdwr_test.sv


filenames: cons/dest/lock/native_handle/requirements/try_lock/try_lock_for/try_lock_until/unlock
filetypes: ddddddddd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/nios2eds/bin/gnu/src/gcc-8.3.1/libstdc++-v3/testsuite/30_threads/timed_mutex


filetypes: fffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/ethernet/alt_ehipc3_fm/example_project/testbench

filenames:
  alt_ehipc3_fm_sl_ptp_chk.sv/checker_fifo.v/pcs_scfifo_mlab.v/reset_timer.v/test_harness.sv/xgmii_sink.sv/xgmii_src.sv


filetypes: fff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/iconnect/alt_hiconnect_traffic_limiter

filenames:
  alt_hiconnect_reorder_memory.sv/alt_hiconnect_traffic_limiter.sv/alt_hiconnect_traffic_limiter_hw.tcl


filenames: pcie_de_ep_dma_g1x8_av_integrated.qsys
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/altera_pcie/altera_pcie_hip_256_avmm/example_design/av


filenames: src_hdl
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filenames:
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filenames: src_hdl
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dirname:
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filenames:
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filetypes: fffffffffff
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dirname:
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filenames:
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filetypes: fffff
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filenames: alt_e100_tx_e10x10_base.v
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filenames: explicit_instantiation
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filenames: reset_csr.v
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filenames: altera_xcvr_native_avgz_wizard.lst/pkgIndex.tcl/presets/tcl
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filetypes: fffffffffffffffffdff
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filenames:
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filetypes: dfffddd
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filenames:
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filenames: alt_vip_common_seq_par_convert.sv
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filenames: arybase.so
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filetypes: dddd
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filenames: alt_mem_if_lpddr2_mem_model.qprs/alt_mem_if_lpddr2_tg_eds_hw.tcl
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filenames: alt_e100_mac.v/common/csr/rx/tx
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filenames: alt_vip_line_stats.sv
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filetypes: ffffffffffffffffffffff
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filenames:
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filetypes: ffffffffffffffffffffffffffffffffd
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filenames:
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filetypes: ffffffffffff
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filenames:
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filenames: ast/csr/efc/mac/pcs/top
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filenames: altera_xcvr_pll_cv_hw.tcl/module.tcl
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dirname:
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  audio/bitec_hdmi_tx.v/bitec_hdmi_tx_aux_encoder.v/bitec_hdmi_tx_aux_encoder_pipeline.v/bitec_hdmi_tx_aux_encoder_wop_gen.v/bitec_hdmi_tx_aux_mux.v/bitec_hdmi_tx_aux_mux_x2.v/bitec_hdmi_tx_create_aux.v/bitec_hdmi_tx_encode.v/bitec_hdmi_tx_resample.v/bitec_hdmi_tx_tmds.v


filenames: alt_vip_vfb_rd_ctrl.ocp/alt_vip_vfb_rd_ctrl.sv
filetypes: ff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/vip/ip_library/component_ip/utility/alt_vip_vfb_rd_ctrl/src_hdl


filenames: Makefile.in/aclocal.m4/configure/configure.in/crt0.s/syscalls.c
filetypes: ffffff
dirname:
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filenames: libwindowplugin.so/qmldir
filetypes: ff
dirname:
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filenames: 2.cc/pod.cc
filetypes: ff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/nios2eds/bin/gnu/src/gcc-8.3.1/libstdc++-v3/testsuite/25_algorithms/reverse_copy/explicit_instantiation


dirname: /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/sld/mm
filetypes: dddddd
filenames:
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filetypes: ffffffffffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/altera_jesd204/src/rx/a10/synopsys

filenames:
  altera_jesd204_rx_base.v/altera_jesd204_rx_csr.v/altera_jesd204_rx_ctl.v/altera_jesd204_rx_descrambler.v/altera_jesd204_rx_dll.v/altera_jesd204_rx_dll_char_val.v/altera_jesd204_rx_dll_cs.v/altera_jesd204_rx_dll_data_store.v/altera_jesd204_rx_dll_ecc_dec.v/altera_jesd204_rx_dll_ecc_enc.v/altera_jesd204_rx_dll_ecc_fifo.v/altera_jesd204_rx_dll_frame_align.v/altera_jesd204_rx_dll_fs_char_replace.v/altera_jesd204_rx_dll_lane_align.v/altera_jesd204_rx_dll_wo_ecc_fifo.v/altera_jesd204_rx_regmap.v


filenames: rtl
filetypes: d
dirname:
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filetypes: ffffffffff
dirname:
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filenames:
  sdi_ii_3gb_demux.v/sdi_ii_descrambler.v/sdi_ii_format.v/sdi_ii_hd_extract_ln.v/sdi_ii_receive.v/sdi_ii_rx_prealign.v/sdi_ii_rx_protocol.v/sdi_ii_sync_bit_rmv.v/sdi_ii_trs_aligner.v/sdi_ii_vpid_extract.v


filenames: eth_ex_100g_sv.qpf/eth_ex_100g_sv.qsf/eth_ex_100g_sv.v
filetypes: fff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/ethernet/alt_eth_ultra/example_project/100g_sv


filetypes: ffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/altera_pcie/altera_pcie_hip_ast_ed/example_design/avgz

filenames:
  pcie_de_gen1_x4_ast64.qsys/pcie_de_gen1_x8_ast128.qsys/pcie_de_gen2_x8_ast256.qsys/pcie_de_gen3_x1_ast64.qsys/pcie_de_gen3_x4_ast128.qsys/pcie_de_gen3_x8_ast256.qsys/pcie_de_rp_gen1_x4_ast64.qsys/pcie_de_rp_gen1_x8_ast128.qsys


filetypes: ffffffffffffffff
dirname:
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filenames:
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filenames: main.tcl/reg_map_inc.tcl
filetypes: ff
dirname:
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filenames: altera_eth_crc.v/crc32.v/gf_mult32_kc.v
filetypes: fff
dirname:
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filenames: alt_e100_phy_pma_a10.v
filetypes: f
dirname:
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filenames: default.mh/default.mt/dos.mh/mips.mt/mn10200.mt/mn10300.mt/ppc.mh/xc16x.mt
filetypes: ffffffff
dirname:
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filenames: alt_vip_common_message_pipeline_stage.sv
filetypes: f
dirname:
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filenames: altera_ldpc_dvb_enc.sv/altera_ldpc_dvb_enc_mat.sv
filetypes: ff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/dsp/altera_ldpc/src/ldpc_ucores/enc/altera_ldpc_dvb_enc/mentor


filetypes: fffffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/altera_dp/src/synopsys/bitec_dp/tx/ss

filenames:
[cell repeats an earlier one in this file: 281 characters]


filetypes: dfffddd
dirname:
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filenames:
  aldec/altera_eth_tse_pcs_pma_gxb.sdc/altera_eth_tse_pcs_pma_gxb.v/altera_eth_tse_pcs_pma_gxb_hw.tcl/cadence/mentor/synopsys


filenames: vcs
filetypes: d
dirname:
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filenames: 1-in.cc/1-io.cc/1-out.cc/1057.cc/2-in.cc/2-io.cc/2-out.cc/59427.cc/9701-2.cc
filetypes: fffffffff
dirname:
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filenames: auk_dspip_crc24ab.vhd/crc_pkg.vhd
filetypes: ff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/dsp/altera_turbo/LTE/src/rtl/crc


filenames: altera_usb_debug_link_hw.tcl/altera_usb_debug_link_internal_hw.tcl
filetypes: ff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/sld/usb/altera_usb_debug_link


filenames: alt_e100_top_sv.qpf/alt_e100_top_sv.qsf/alt_e100_top_sv.v
filetypes: fff
dirname:
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filetypes: fffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/altera_onchip_flash/altera_onchip_flash/mentor

filenames:
[cell repeats an earlier one in this file: 259 characters]


filenames: intel_pcie_schd_order.sv/intel_pcie_schd_piped_empty_calc.sv/intel_pcie_schd_scfifo.sv
filetypes: fff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/intel_pcie/avmm_bridge_512/schd/common


filetypes: fffffffffffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/quartus/common/tcl/packages/tcllib-1.11/example/csv

filenames:
  Bench.csv/Bench.html/Benchmark.75p2.csv/Benchmark.76p2.csv/Benchmark.805.csv/Benchmark.811.csv/Benchmark.823.csv/Benchmark.833.csv/Benchmark.84a3.csv/README/bench_join/csv2html/csvcut/csvdiff/csvjoin/csvsort/csvuniq


filetypes: ffffffffffffffff
dirname:
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filenames:
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dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/ethernet/alt_e25s10/hslx/synopsys

filenames:
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filetypes:
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filetypes: ffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/alt_xcvr/altera_xcvr_reset_control/tcl

filenames:
  altera_xcvr_reset_control_hw.tcl/arria10_default.qprs/arria10_no_sequencing.qprs/default.qprs/fileset.tcl/interfaces.tcl/module.tcl/parameters.tcl


filenames: swap.cc/swap_cxx17.cc
filetypes: ff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/nios2eds/bin/gnu/src/gcc-8.3.1/libstdc++-v3/testsuite/23_containers/array/specialized_algorithms


filenames: 1.cc/18654.cc/2.cc/shrink_to_fit.cc
filetypes: ffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/nios2eds/bin/gnu/src/gcc-8.3.1/libstdc++-v3/testsuite/21_strings/basic_string/capacity/wchar_t


filenames: synopsis.cc/types_std_c++0x.cc/using_namespace_std_placeholders.cc
filetypes: fff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/nios2eds/bin/gnu/src/gcc-8.3.1/libstdc++-v3/testsuite/20_util/headers/functional


filenames: cons/operators/requirements
filetypes: ddd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/nios2eds/bin/gnu/src/gcc-8.3.1/libstdc++-v3/testsuite/26_numerics/random/bernoulli_distribution


filenames: ccip_cfg_pkg.sv/hssi_cfg_pkg.sv/local_mem_cfg_pkg.sv
filetypes: fff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/board/intel_s10sx_pac/hardware/pac_s10_usm/build/platform_if/rtl/device_cfg


filenames: 1.cc/2.cc/29354.cc/3.cc
filetypes: ffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/nios2eds/bin/gnu/src/gcc-8.3.1/libstdc++-v3/testsuite/27_io/basic_stringbuf/seekpos/wchar_t


dirname: /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/emif/ip_soft_nios
filetypes: ffffffffff
filenames:
  altera_emif_soft_nios_hw.tcl/common_gui.properties/common_messages.properties/common_params.properties/common_ports.properties/gui.properties/main.tcl/messages.properties/soft_nios_onchip_memory_nd.hex/soft_nios_onchip_memory_nf.hex


filenames: moveable.cc/requirements
filetypes: fd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/nios2eds/bin/gnu/src/gcc-8.3.1/libstdc++-v3/testsuite/25_algorithms/reverse


filenames: alt_mge_xcvr_atx_pll_10g_s10_h.ip/alt_mge_xcvr_atx_pll_10g_s10_l.ip
filetypes: ff
dirname:
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aldec/alt_e2550_a10mlab.sv/alt_e2550_acc10t1.v/alt_e2550_aclr_filter.v/alt_e2550_add3t1e.v/alt_e2550_add4t1.v/alt_e2550_add4t1e.v/alt_e2550_add6t1.v/alt_e2550_add6t1e.v/alt_e2550_add7t1e.v/alt_e2550_add7t1ec.v/alt_e2550_addc1h1t1.v/alt_e2550_addc2h0t1.v/alt_e2550_addc2h1t1.v/alt_e2550_addc2h2t1.v/alt_e2550_addc2h3t1.v/alt_e2550_addc3h2t1.v/alt_e2550_addc3h3t1.v/alt_e2550_addc3h4t1.v/alt_e2550_addc3h5t1.v/alt_e2550_addc4h3t1.v/alt_e2550_addc4h4t1.v/alt_e2550_addc4h5t1.v/alt_e2550_addc4h6t1.v/alt_e2550_addc4h9t1.v/alt_e2550_addc5h03t1.v/alt_e2550_addc5h05t1.v/alt_e2550_addc5h10t1.v/alt_e2550_addc5h11t1.v/alt_e2550_addc5h1ft1.v/alt_e2550_adder.v/alt_e2550_alignmon32768e8.v/alt_e2550_alignmon512e8.v/alt_e2550_and11t2.v/alt_e2550_and2t0.v/alt_e2550_and2t1.v/alt_e2550_and3t0.v/alt_e2550_and3t1.v/alt_e2550_and4t0.v/alt_e2550_and4t1.v/alt_e2550_and5t0.v/alt_e2550_and5t1.v/alt_e2550_and6t0.v/alt_e2550_and6t1.v/alt_e2550_and8t2.v/alt_e2550_and9t2.v/alt_e2550_avmm_dummy.v/alt_e2550_band2w20t1.v/alt_e2550_bytecnt16.v/alt_e2550_bytecnt8.v/alt_e2550_cnt10.v/alt_e2550_cnt10c.v/alt_e2550_cnt2.v/alt_e2550_cnt2c.v/alt_e2550_cnt3.v/alt_e2550_cnt3c.v/alt_e2550_cnt3ic.v/alt_e2550_cnt4.v/alt_e2550_cnt4c.v/alt_e2550_cnt4cd.v/alt_e2550_cnt4i.v/alt_e2550_cnt4ic.v/alt_e2550_cnt5.v/alt_e2550_cnt5c.v/alt_e2550_cnt6.v/alt_e2550_cnt6c.v/alt_e2550_cnt6cd.v/alt_e2550_cnt6i.v/alt_e2550_cnt6ic.v/alt_e2550_cnt8c.v/alt_e2550_cnt8ci.v/alt_e2550_cnt8i.v/alt_e2550_cntm1m2c.v/alt_e2550_compress16t3.v/alt_e2550_compress4t1.v/alt_e2550_compress8t2.v/alt_e2550_compressor_4to3.v/alt_e2550_crc32_acc_1_t2.v/alt_e2550_crc32_acc_2_t2.v/alt_e2550_crc32_da_1_t3.v/alt_e2550_crc32_da_2_t6.v/alt_e2550_crc32_f_1_t12.v/alt_e2550_crc32_f_2_t15.v/alt_e2550_crc32_rb_1_t2.v/alt_e2550_crc32_rb_2_t2.v/alt_e2550_crc32_rb_4_t2.v/alt_e2550_crc32_rba_t6.v/alt_e2550_crc32_s64_t2.v/alt_e2550_crc32_w_1_t6.v/alt_e2550_crc32_w_2_t9.v/alt_e2550_crc32_z64_1_t2.v/alt_e2550_crc32_z64_2_t2.v/alt_e2550_crccmp32w1t3.v/alt_e2550_crccmp32w2t3.v/alt_e2550_crcpt.v/alt_e2550_cumeary32w10.v/alt_e2550_dec32t1.v/alt_e2550_dec4t1.v/alt_e2550_delay10w32c.v/alt_e2550_delay10w4.v/alt_e2550_delay10w5c.v/alt_e2550_delay10w64c.v/alt_e2550_delay11w1.v/alt_e2550_delay13w32.v/alt_e2550_delay13w64.v/alt_e2550_delay13w8.v/alt_e2550_delay14w1.v/alt_e2550_delay14w2.v/alt_e2550_delay14w64.v/alt_e2550_delay15w1.v/alt_e2550_delay15w64c.v/alt_e2550_delay16w1.v/alt_e2550_delay16w64.v/alt_e2550_delay17w1.v/alt_e2550_delay17w3.v/alt_e2550_delay18w1.v/alt_e2550_delay18w2.v/alt_e2550_delay18w64.v/alt_e2550_delay19w2.v/alt_e2550_delay19w64.v/alt_e2550_delay1w1.v/alt_e2550_delay1w2.v/alt_e2550_delay1w4.v/alt_e2550_delay20w1.v/alt_e2550_delay20w3.v/alt_e2550_delay22w1.v/alt_e2550_delay22w3.v/alt_e2550_delay25w1.v/alt_e2550_delay25w3.v/alt_e2550_delay26w1.v/alt_e2550_delay27w1.v/alt_e2550_delay27w3.v/alt_e2550_delay2w1.v/alt_e2550_delay2w2.v/alt_e2550_delay2w34.v/alt_e2550_delay2w4.v/alt_e2550_delay2w5.v/alt_e2550_delay2w9.v/alt_e2550_delay3w1.v/alt_e2550_delay3w2.v/alt_e2550_delay3w34.v/alt_e2550_delay3w6.v/alt_e2550_delay3w64.v/alt_e2550_delay3w64c.v/alt_e2550_delay4w1.v/alt_e2550_delay4w2.v/alt_e2550_delay4w44c.v/alt_e2550_delay4w64.v/alt_e2550_delay5w1.v/alt_e2550_delay5w2.v/alt_e2550_delay5w44.v/alt_e2550_delay5w64.v/alt_e2550_delay6w1.v/alt_e2550_delay6w11.v/alt_e2550_delay6w3.v/alt_e2550_delay6w6.v/alt_e2550_delay6w64.v/alt_e2550_delay6w64c.v/alt_e2550_delay7w44.v/alt_e2550_delay8w1.v/alt_e2550_delay8w44.v/alt_e2550_delay9w6.v/alt_e2550_delay_dynamic.v/alt_e2550_delay_reg.v/alt_e2550_descram128.v/alt_e2550_descram64.v/alt_e2550_dip8_32.v/alt_e2550_dlv66.v/alt_e2550_ebip2.v/alt_e2550_ecrcins.v/alt_e2550_edesk4.v/alt_e2550_eq18t2.v/alt_e2550_eq20t3.v/alt_e2550_eq2t0.v/alt_e2550_eq2t1.v/alt_e2550_eq32t3.v/alt_e2550_eq3t0.v/alt_e2550_eq3t1.v/alt_e2550_eq4t1.v/alt_e2550_eq8t1.v/alt_e2550_eq9t1.v/alt_e2550_eq9t2.v/alt_e2550_eq_10_const.v/alt_e2550_eq_5_ena.v/alt_e2550_eqc11h4fbt2.v/alt_e2550_eqc15h7cfbt2.v/alt_e2550_eqc15h7fe8t2.v/alt_e2550_eqc15h7ffbt2.v/alt_e2550_eqc17h13ffbt2.v/alt_e2550_eqc19h4e1fbt2.v/alt_e2550_eqc4h0t1.v/alt_e2550_eqc4h5t1.v/alt_e2550_eqc4h9t1.v/alt_e2550_eqc4hft1.v/alt_e2550_eqc54h00555555555555t3.v/alt_e2550_eqc5h07t1.v/alt_e2550_eqc5h08t1.v/alt_e2550_eqc5h0dt1.v/alt_e2550_eqc5h0ft1.v/alt_e2550_eqc5h13t1.v/alt_e2550_eqc5h18t1.v/alt_e2550_eqc5h1bt1.v/alt_e2550_eqc5h1bt1e.v/alt_e2550_eqc5h1dt1.v/alt_e2550_eqc5h1dt1e.v/alt_e2550_eqc5h1ft1.v/alt_e2550_eqc6h00t1.v/alt_e2550_eqc6h15t1.v/alt_e2550_eqc6h3bt1.v/alt_e2550_eqc6h3ft1.v/alt_e2550_eqc8h00t2.v/alt_e2550_eqc9h0d5t2.v/alt_e2550_eqc9h1e8t2.v/alt_e2550_eqc9h1fbt2.v/alt_e2550_eqc9h1fdt2.v/alt_e2550_etag2_20_22.v/alt_e2550_etag2_21_23.v/alt_e2550_etagid.v/alt_e2550_etagro4.v/alt_e2550_ethdec.v/alt_e2550_ethenc.v/alt_e2550_extended_stats_vector.v/alt_e2550_fd07ins.v/alt_e2550_flagover1t2.v/alt_e2550_flagover2t2.v/alt_e2550_fmon2.v/alt_e2550_fmon3.v/alt_e2550_fmon8.v/alt_e2550_frame_1024to1518b.v/alt_e2550_frame_128to255b.v/alt_e2550_frame_1519tom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e2550_tx_fc_pb_conv.v/alt_e2550_tx_fc_pb_timer.v/alt_e2550_txmon.v/alt_e2550_watchdog16.v/alt_e2550_wdly33.v/alt_e2550_wys_lut.v/alt_e2550_xor1t0.v/alt_e2550_xor1t1.v/alt_e2550_xor2t0.v/alt_e2550_xor2t1.v/alt_e2550_xor3t0.v/alt_e2550_xor3t1.v/alt_e2550_xor4t0.v/alt_e2550_xor4t1.v/alt_e2550_xor5t0.v/alt_e2550_xor5t1.v/alt_e2550_xor6t0.v/alt_e2550_xor6t1.v/alt_e2550_xrise1r3.v/alt_e25s10_etag.v/alt_e25s10_ethdec.v/alt_e25s10_ethenc.v/alt_e25s10_frmwatch.v/alt_e25s10_rxmon.v/alt_e25s10_txmon.v/cadence/latency_pulse_measurement.v/latency_pulse_measurement_top.v/mentor/synopsys

filetypes:
  dfffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffdffdd


filenames: altera_up_avalon_de1_soc_adc.c
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/university_program/input_output/altera_up_avalon_de1_soc_adc/HAL/src


filetypes: fffffffffffffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/alt_eth_40g_100g/40gbe/rtl_src/phy/aldec/pcs/rx

filenames:
  alt_e40_block_decoder.v/alt_e40_block_decoder_ns.v/alt_e40_descrambler.v/alt_e40_framed_descrambler.v/alt_e40_gearbox_40_66.v/alt_e40_lane_marker_compare.v/alt_e40_lane_marker_lock.v/alt_e40_mii_decode_multiple.v/alt_e40_pcs_ber.v/alt_e40_pcs_ber_cnt_ns.v/alt_e40_pcs_ber_sm.v/alt_e40_pcs_rx.v/alt_e40_pcs_rx_testmode.v/alt_e40_prbs_rx.v/alt_e40_reorder_destripe.v/alt_e40_rx_lane.v/alt_e40_rx_lane_array.v/alt_e40_rx_nav_region.v/alt_e40_word_align_control.v


filetypes: ffffffffffffffffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/ip/altera/seriallite4/ed/ed_synth/src/demo_control

filenames:
  Readme.txt/build_demo_control.sh.terp/demo_control_clock_bridge_0.ip/demo_control_duplex.qsys/demo_control_in_system_sources_probes_0.ip/demo_control_master_0.ip/demo_control_master_1.ip/demo_control_mm_bridge_0.ip/demo_control_mm_bridge_1.ip/demo_control_pio_0.ip/demo_control_pio_1.ip/demo_control_pio_2.ip/demo_control_pio_3.ip/demo_control_pio_4.ip/demo_control_reset_bridge_0.ip/demo_control_reset_bridge_1.ip/demo_control_simplex.qsys/dp_hs_req.v/dp_hs_resp.v/measure_payload_pio_l_0.ip/system_status_pio_0.ip/tx_lanes_status_pio_0.ip


filenames: 66055.cc/deduction.cc/moveable.cc
filetypes: fff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/nios2eds/bin/gnu/src/gcc-8.3.1/libstdc++-v3/testsuite/23_containers/unordered_multimap/cons


dirname: /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/nios2eds/documents/gnu-tools/ld.html
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l/arriav_soc_interface_f2s_interrupts_info.xml/arriav_soc_interface_fpga2sdram_info.xml/arriav_soc_interface_fpga2soc_info.xml/arriav_soc_interface_gp_info.xml/arriav_soc_interface_peripheral_emac_info.xml/arriav_soc_interface_peripheral_i2c_info.xml/arriav_soc_interface_peripheral_nand_info.xml/arriav_soc_interface_peripheral_qspi_info.xml/arriav_soc_interface_peripheral_sdio_info.xml/arriav_soc_interface_peripheral_spi_info.xml/arriav_soc_interface_peripheral_uart_info.xml/arriav_soc_interface_peripheral_usb_info.xml/arriav_soc_interface_s2f_debug_apb_info.xml/arriav_soc_interface_s2f_interrupts_info.xml/arriav_soc_interface_soc2fpga_info.xml/arriav_soc_interface_soc_loaned_io_info.xml/arriav_soc_interface_trace_fpga_info.xml/arriav_soc_interface_trace_tpiu_info.xml/arriav_termination_info.xml/arriav_termination_logic_info.xml/arriav_tsdblock_info.xml/arriav_vfifo_info.xml/arriavgz_asmiblock_info.xml/arriavgz_att_cdr_pll_info.xml/arriavgz_atx_pll_info.xml/arriavgz_bias_block_info.xml/arriavgz_channel_pll_info.xml/arriavgz_chipidblock_info.xml/arriavgz_clk_phase_select_info.xml/arriavgz_clkburst_info.xml/arriavgz_clkena_info.xml/arriavgz_clkselect_info.xml/arriavgz_controller_info.xml/arriavgz_crcblock_info.xml/arriavgz_cvpcieblock_info.xml/arriavgz_ddio_in_info.xml/arriavgz_ddio_oe_info.xml/arriavgz_ddio_out_info.xml/arriavgz_delay_chain_info.xml/arriavgz_dftblock_info.xml/arriavgz_dll_info.xml/arriavgz_dll_offset_ctrl_info.xml/arriavgz_dqs_config_info.xml/arriavgz_dqs_delay_chain_info.xml/arriavgz_dqs_enable_ctrl_info.xml/arriavgz_duty_cycle_adjustment_info.xml/arriavgz_ff_info.xml/arriavgz_fractional_pll_info.xml/arriavgz_half_rate_input_info.xml/arriavgz_input_phase_alignment_info.xml/arriavgz_io_clock_divider_info.xml/arriavgz_io_config_info.xml/arriavgz_io_ibuf_info.xml/arriavgz_io_obuf_info.xml/arriavgz_io_pad_info.xml/arriavgz_jtag_info.xml/arriavgz_lcell_comb_info.xml/arriavgz_leveling_delay_chain_info.xml/arriavgz_lvds_rx_info.xml/arriavgz_lvds_tx_info.xml/arriavgz_mac_info.xml/arriavgz_mlab_cell_info.xml/arriavgz_opregblock_info.xml/arriavgz_oscillator_info.xml/arriavgz_output_alignment_info.xml/arriavgz_phb_info.xml/arriavgz_phy_clkbuf_info.xml/arriavgz_pll_dll_output_info.xml/arriavgz_pll_dpa_output_info.xml/arriavgz_pll_extclk_output_info.xml/arriavgz_pll_lvds_output_info.xml/arriavgz_pll_output_counter_info.xml/arriavgz_pll_reconfig_info.xml/arriavgz_pll_refclk_select_info.xml/arriavgz_prblock_info.xml/arriavgz_pseudo_diff_out_info.xml/arriavgz_ram_block_info.xml/arriavgz_read_fifo_info.xml/arriavgz_read_fifo_read_enable_info.xml/arriavgz_rublock_info.xml/arriavgz_termination_info.xml/arriavgz_termination_logic_info.xml/arriavgz_tsdblock_info.xml/bedrock_clkena_info.xml/bedrock_clkselect_info.xml/bedrock_ff_info.xml/bedrock_io_ibuf_info.xml/bedrock_io_obuf_info.xml/bedrock_io_pad_info.xml/bedrock_lcell_comb_info.xml/bedrock_mac_info.xml/bedrock_mlab_cell_info.xml/bedrock_phy_clkbuf_info.xml/bedrock_ram_block_info.xml/cbxi_regen_rules.xml/ctm_tile_info.xml/cyclone10gx_asmiblock_info.xml/cyclone10gx_atx_pll_info.xml/cyclone10gx_bias_block_info.xml/cyclone10gx_clkburst_info.xml/cyclone10gx_clkena_info.xml/cyclone10gx_clkselect_info.xml/cyclone10gx_cmu_fpll_info.xml/cyclone10gx_cmu_fpll_refclk_select_info.xml/cyclone10gx_controller_info.xml/cyclone10gx_crcblock_info.xml/cyclone10gx_cvpcieblock_info.xml/cyclone10gx_ddio_in_info.xml/cyclone10gx_ddio_oe_info.xml/cyclone10gx_ddio_out_info.xml/cyclone10gx_delay_chain_info.xml/cyclone10gx_dftblock_info.xml/cyclone10gx_ff_info.xml/cyclone10gx_fp_mac_info.xml/cyclone10gx_hps_interface_boot_from_fpga_info.xml/cyclone10gx_hps_interface_clocks_resets_info.xml/cyclone10gx_hps_interface_cross_trigger_info.xml/cyclone10gx_hps_interface_dbg_apb_info.xml/cyclone10gx_hps_interface_ddr_info.xml/cyclone10gx_hps_interface_dma_info.xml/cyclone10gx_hps_interface_emac_switch_info.xml/cyclone10gx_hps_interface_fpga2hps_info.xml/cyclone10gx_hps_interface_fpga2sdram_info.xml/cyclone10gx_hps_interface_hps2fpga_info.xml/cyclone10gx_hps_interface_hps2fpga_light_weight_info.xml/cyclone10gx_hps_interface_interrupts_info.xml/cyclone10gx_hps_interface_jtag_info.xml/cyclone10gx_hps_interface_mpu_event_standby_info.xml/cyclone10gx_hps_interface_mpu_general_purpose_info.xml/cyclone10gx_hps_interface_peripheral_emac_info.xml/cyclone10gx_hps_interface_peripheral_i2c_info.xml/cyclone10gx_hps_interface_peripheral_nand_info.xml/cyclone10gx_hps_interface_peripheral_qspi_info.xml/cyclone10gx_hps_interface_peripheral_sdmmc_info.xml/cyclone10gx_hps_interface_peripheral_spi_master_info.xml/cyclone10gx_hps_interface_peripheral_spi_slave_info.xml/cyclone10gx_hps_interface_peripheral_uart_info.xml/cyclone10gx_hps_interface_peripheral_usb_info.xml/cyclone10gx_hps_interface_security_module_info.xml/cyclone10gx_hps_interface_stm_event_info.xml/cyclone10gx_hps_interface_test_info.xml/cyclone10gx_hps_interface_tpiu_trace_info.xml/cyclone10gx_hps_peripheral_can_info.xml/cyclone10gx_hps_peripheral_emac_info.xml/cyclone10gx_hps_peripheral_gpio_info.xml/cyclone10gx_hps_peripheral_i2c_info.xml/cyclone10gx_hps_peripheral_nand_info.xml/cyclone10gx_hps_peripheral_pll_clk_info.xml/cyclone10gx_hps_peripheral_qspi_info.xml/cyclone10gx_hps_peripheral_sdmmc_info.xml/cyclone10gx_hps_peripheral_spi_master_info.xml/cyclone10gx_hps_peripheral_spi_slave_info.xml/cyclone10gx_hps_peripheral_tpiu_trace_info.xml/cyclone10gx_hps_peripheral_uart_info.xml/cyclone10gx_hps_peripheral_usb_info.xml/cyclone10gx_io_12_lane_info.xml/cyclone10gx_io_aux_info.xml/cyclone10gx_io_ibuf_info.xml/cyclone10gx_io_obuf_info.xml/cyclone10gx_io_pad_info.xml/cyclone10gx_io_serdes_dpa_info.xml/cyclone10gx_iopll_info.xml/cyclone10gx_jtag_info.xml/cyclone10gx_jtagblock_info.xml/cyclone10gx_lcell_comb_info.xml/cyclone10gx_lvds_clock_tree_info.xml/cyclone10gx_mac_info.xml/cyclone10gx_mlab_cell_info.xml/cyclone10gx_opregblock_info.xml/cyclone10gx_oscillator_info.xml/cyclone10gx_prblock_info.xml/cyclone10gx_pseudo_diff_out_info.xml/cyclone10gx_ram_block_info.xml/cyclone10gx_refclk_input_info.xml/cyclone10gx_rublock_info.xml/cyclone10gx_te_test_atom_info.xml/cyclone10gx_termination_info.xml/cyclone10gx_termination_logic_info.xml/cyclone10gx_tile_ctrl_info.xml/cyclone10gx_tsdblock_info.xml/cyclone10gx_uib_rdrc_cell_info.xml/cyclone10gx_uib_wdrc_cell_info.xml/cyclone10gx_vsblock_info.xml/cyclone_crcblock_info.xml/cyclone_io_info.xml/cyclone_jtag_info.xml/cyclone_lcell_info.xml/cyclone_pll_info.xml/cyclone_ram_block_info.xml/cycloneii_clkctrl_info.xml/cycloneii_crcblock_info.xml/cycloneii_jtag_info.xml/cycloneii_pll_info.xml/cycloneii_ram_block_info.xml/cycloneiii_apfcontroller_info.xml/cycloneiii_clkctrl_info.xml/cycloneiii_crcblock_info.xml/cycloneiii_ddio_oe_info.xml/cycloneiii_ddio_out_info.xml/cycloneiii_ff_info.xml/cycloneiii_io_ibuf_info.xml/cycloneiii_io_obuf_info.xml/cycloneiii_io_pad_info.xml/cycloneiii_jtag_info.xml/cycloneiii_lcell_comb_info.xml/cycloneiii_mac_mult_info.xml/cycloneiii_mac_out_info.xml/cycloneiii_oscillator_info.xml/cycloneiii_pll_info.xml/cycloneiii_pseudo_diff_out_info.xml/cycloneiii_ram_block_info.xml/cycloneiii_rublock_info.xml/cycloneiii_termination_info.xml/cycloneiiils_clkctrl_info.xml/cycloneiiils_controller_info.xml/cycloneiiils_crcblock_info.xml/cycloneiiils_ddio_oe_info.xml/cycloneiiils_ddio_out_info.xml/cycloneiiils_ff_info.xml/cycloneiiils_io_ibuf_info.xml/cycloneiiils_io_obuf_info.xml/cycloneiiils_io_pad_info.xml/cycloneiiils_jtag_info.xml/cycloneiiils_lcell_comb_info.xml/cycloneiiils_mac_mult_info.xml/cycloneiiils_mac_out_info.xml/cycloneiiils_opregblock_info.xml/cycloneiiils_oscillator_info.xml/cycloneiiils_pll_info.xml/cycloneiiils_pseudo_diff_out_info.xml/cycloneiiils_ram_block_info.xml/cycloneiiils_rublock_info.xml/cycloneiiils_termination_info.xml/cycloneiiils_testaccessblock_info.xml/cycloneiiils_volatilekeyblock_info.xml/cycloneiv_clkctrl_info.xml/cycloneiv_controller_info.xml/cycloneiv_crcblock_info.xml/cycloneiv_ddio_oe_info.xml/cycloneiv_ddio_out_info.xml/cycloneiv_ff_info.xml/cycloneiv_io_ibuf_info.xml/cycloneiv_io_obuf_info.xml/cycloneiv_io_pad_info.xml/cycloneiv_jtag_info.xml/cycloneiv_lcell_comb_info.xml/cycloneiv_mac_mult_info.xml/cycloneiv_mac_out_info.xml/cycloneiv_oscillator_info.xml/cycloneiv_pll_info.xml/cycloneiv_pseudo_diff_out_info.xml/cycloneiv_ram_block_info.xml/cycloneiv_rublock_info.xml/cycloneiv_termination_info.xml/cycloneive_apfcontroller_info.xml/cycloneive_clkctrl_info.xml/cycloneive_crcblock_info.xml/cycloneive_ddio_oe_info.xml/cycloneive_ddio_out_info.xml/cycloneive_ff_info.xml/cycloneive_io_ibuf_info.xml/cycloneive_io_obuf_info.xml/cycloneive_io_pad_info.xml/cycloneive_jtag_info.xml/cycloneive_lcell_comb_info.xml/cycloneive_mac_mult_info.xml/cycloneive_mac_out_info.xml/cycloneive_oscillator_info.xml/cycloneive_pll_info.xml/cycloneive_pseudo_diff_out_info.xml/cycloneive_ram_block_info.xml/cycloneive_rublock_info.xml/cycloneive_termination_info.xml/cyclonev_asmiblock_info.xml/cyclonev_bias_block_info.xml/cyclonev_channel_pll_info.xml/cyclonev_chipidblock_info.xml/cyclonev_clk_phase_select_info.xml/cyclonev_clkburst_info.xml/cyclonev_clkena_info.xml/cyclonev_clkselect_info.xml/cyclonev_controller_info.xml/cyclonev_crcblock_info.xml/cyclonev_cvpcieblock_info.xml/cyclonev_ddio_in_info.xml/cyclonev_ddio_oe_info.xml/cyclonev_ddio_out_info.xml/cyclonev_delay_chain_info.xml/cyclonev_dftblock_info.xml/cyclonev_dll_info.xml/cyclonev_dqs_config_info.xml/cyclonev_dqs_delay_chain_info.xml/cyclonev_dqs_enable_ctrl_info.xml/cyclonev_ff_info.xml/cyclonev_fractional_pll_info.xml/cyclonev_hd_altpe2_hip_top_info.xml/cyclonev_hmc_info.xml/cyclonev_hps_interface_boot_from_fpga_info.xml/cyclonev_hps_interface_clocks_resets_info.xml/cyclonev_hps_interface_cross_trigger_info.xml/cyclonev_hps_interface_dma_info.xml/cyclonev_hps_interface_fpga2hps_info.xml/cyclonev_hps_interface_fpga2sdram_info.xml/cyclonev_hps_interface_hps2fpga_info.xml/cyclonev_hps_interface_hps2fpga_light_weight_info.xml/cyclonev_hps_interface_interrupts_info.xml/cyclonev_hps_interface_jtag_info.xml/cyclonev_hps_interface_loan_io_info.xml/cyclonev_hps_interface_mpu_event_standby_info.xml/cyclonev_hps_interface_mpu_general_purpose_info.xml/cyclonev_hps_interface_peripheral_can_info.xml/cyclonev_hps_interface_peripheral_emac_info.xml/cyclonev_hps_interface_peripheral_i2c_info.xml/cyclonev_hps_interface_peripheral_nand_info.xml/cyclonev_hps_interface_peripheral_qspi_info.xml/cyclonev_hps_interface_peripheral_sdmmc_info.xml/cyclonev_hps_interface_peripheral_spi_master_info.xml/cyclonev_hps_interface_peripheral_spi_slave_info.xml/cyclonev_hps_interface_peripheral_uart_info.xml/cyclonev_hps_interface_peripheral_usb_info.xml/cyclonev_hps_interface_stm_event_info.xml/cyclonev_hps_interface_tpiu_trace_info.xml/cyclonev_hps_sdram_pll_info.xml/cyclonev_io_config_info.xml/cyclonev_io_ibuf_info.xml/cyclonev_io_obuf_info.xml/cyclonev_io_pad_info.xml/cyclonev_ir_fifo_userdes_info.xml/cyclonev_jtag_info.xml/cyclonev_lcell_comb_info.xml/cyclonev_leveling_delay_chain_info.xml/cyclonev_lfifo_info.xml/cyclonev_mac_info.xml/cyclonev_mem_phy_info.xml/cyclonev_mlab_cell_info.xml/cyclonev_opregblock_info.xml/cyclonev_oscillator_info.xml/cyclonev_phy_clkbuf_info.xml/cyclonev_pll_aux_info.xml/cyclonev_pll_dll_output_info.xml/cyclonev_pll_dpa_output_info.xml/cyclonev_pll_extclk_output_info.xml/cyclonev_pll_lvds_output_info.xml/cyclonev_pll_output_counter_info.xml/cyclonev_pll_reconfig_info.xml/cyclonev_pll_refclk_select_info.xml/cyclonev_prblock_info.xml/cyclonev_pseudo_diff_out_info.xml/cyclonev_ram_block_info.xml/cyclonev_read_fifo_read_clock_select_info.xml/cyclonev_rublock_info.xml/cyclonev_s2f_clk_r_mux_info.xml/cyclonev_s2f_clk_t_mux_info.xml/cyclonev_soc_interface_dma_info.xml/cyclonev_soc_interface_f2s_debug_apb_info.xml/cyclonev_soc_interface_f2s_interrupts_info.xml/cyclonev_soc_interface_fpga2sdram_info.xml/cyclonev_soc_interface_fpga2soc_info.xml/cyclonev_soc_interface_gp_info.xml/cyclonev_soc_interface_peripheral_emac_info.xml/cyclonev_soc_interface_peripheral_i2c_info.xml/cyclonev_soc_interface_peripheral_nand_info.xml/cyclonev_soc_interface_peripheral_qspi_info.xml/cyclonev_soc_interface_peripheral_sdio_info.xml/cyclonev_soc_interface_peripheral_spi_info.xml/cyclonev_soc_interface_peripheral_uart_info.xml/cyclonev_soc_interface_peripheral_usb_info.xml/cyclonev_soc_interface_s2f_debug_apb_info.xml/cyclonev_soc_interface_s2f_interrupts_info.xml/cyclonev_soc_interface_soc2fpga_info.xml/cyclonev_soc_interface_soc_loaned_io_info.xml/cyclonev_soc_interface_trace_fpga_info.xml/cyclonev_soc_interface_trace_tpiu_info.xml/cyclonev_termination_info.xml/cyclonev_termination_logic_info.xml/cyclonev_vfifo_info.xml/dcfifo_info.xml/dcfifo_mixed_widths_info.xml/dcfifo_rules.xml/dcfifo_wiz_map.xml/fourteennm_aux_master_info.xml/fourteennm_clk_burst_info.xml/fourteennm_clk_divider_info.xml/fourteennm_clk_gate_info.xml/fourteennm_clk_select_info.xml/fourteennm_cpa_info.xml/fourteennm_ddio_in_info.xml/fourteennm_ddio_oe_info.xml/fourteennm_ddio_out_info.xml/fourteennm_dib_io_wrp_info.xml/fourteennm_dib_phy_info.xml/fourteennm_dibss_aux_info.xml/fourteennm_dibssm_info.xml/fourteennm_esram_info.xml/fourteennm_ff_info.xml/fourteennm_fp_mac_info.xml/fourteennm_hbmc_info.xml/fourteennm_hps_fpga2hps_info.xml/fourteennm_hps_interface_clocks_resets_info.xml/fourteennm_hps_interface_cross_trigger_info.xml/fourteennm_hps_interface_dbg_apb_info.xml/fourteennm_hps_interface_ddr_info.xml/fourteennm_hps_interface_dma_info.xml/fourteennm_hps_interface_emac_switch_info.xml/fourteennm_hps_interface_fpga2hps_info.xml/fourteennm_hps_interface_fpga2sdram_info.xml/fourteennm_hps_interface_hps2fpga_info.xml/fourteennm_hps_interface_hps2fpga_light_weight_info.xml/fourteennm_hps_interface_interrupts_info.xml/fourteennm_hps_interface_jtag_info.xml/fourteennm_hps_interface_loan_io_info.xml/fourteennm_hps_interface_mpfe_info.xml/fourteennm_hps_interface_mpu_event_standby_info.xml/fourteennm_hps_interface_mpu_general_purpose_info.xml/fourteennm_hps_interface_peripheral_emac_info.xml/fourteennm_hps_interface_peripheral_i2c_info.xml/fourteennm_hps_interface_peripheral_nand_info.xml/fourteennm_hps_interface_peripheral_sdmmc_info.xml/fourteennm_hps_interface_peripheral_spi_master_info.xml/fourteennm_hps_interface_peripheral_spi_slave_info.xml/fourteennm_hps_interface_peripheral_uart_info.xml/fourteennm_hps_interface_stm_event_info.xml/fourteennm_hps_interface_test_info.xml/fourteennm_hps_interface_tpiu_trace_info.xml/fourteennm_hps_mpfe_interface_info.xml/fourteennm_hps_mpfe_interrupts_info.xml/fourteennm_hps_mpfe_test_info.xml/fourteennm_hps_peripheral_emac_info.xml/fourteennm_hps_peripheral_gpio_info.xml/fourteennm_hps_peripheral_i2c_info.xml/fourteennm_hps_peripheral_nand_info.xml/fourteennm_hps_peripheral_pll_clk_info.xml/fourteennm_hps_peripheral_qspi_info.xml/fourteennm_hps_peripheral_sdmmc_info.xml/fourteennm_hps_peripheral_spi_master_info.xml/fourteennm_hps_peripheral_spi_slave_info.xml/fourteennm_hps_peripheral_tpiu_trace_info.xml/fourteennm_hps_peripheral_uart_info.xml/fourteennm_hps_peripheral_usb_info.xml/fourteennm_io_12_lane_info.xml/fourteennm_io_aux_info.xml/fourteennm_io_ibuf_info.xml/fourteennm_io_obuf_info.xml/fourteennm_io_pad_info.xml/fourteennm_io_serdes_dpa_info.xml/fourteennm_iopll_info.xml/fourteennm_iossm_info.xml/fourteennm_lcell_comb_info.xml/fourteennm_logic_module_info.xml/fourteennm_logical_pll_info.xml/fourteennm_lsm_avmm_master_info.xml/fourteennm_lsm_avmm_slave_info.xml/fourteennm_lsm_bf_info.xml/fourteennm_lsm_gpio_in_info.xml/fourteennm_lsm_gpio_intr_info.xml/fourteennm_lsm_gpio_out_info.xml/fourteennm_lsm_soft_logic_reset_info.xml/fourteennm_lvds_clock_tree_info.xml/fourteennm_mac_info.xml/fourteennm_mlab_cell_info.xml/fourteennm_pseudo_diff_out_info.xml/fourteennm_ram_block_info.xml/fourteennm_refclk_input_info.xml/fourteennm_sdm_aux_iossm_info.xml/fourteennm_sdm_axi_fpga2sdm_info.xml/fourteennm_sdm_axi_sdm2fpga_info.xml/fourteennm_sdm_dftblock_info.xml/fourteennm_sdm_fpga_core_rst_info.xml/fourteennm_sdm_gpio_in_info.xml/fourteennm_sdm_gpio_intr_info.xml/fourteennm_sdm_gpio_intr_out_info.xml/fourteennm_sdm_gpio_out_info.xml/fourteennm_sdm_jtag_ela_info.xml/fourteennm_sdm_jtag_mon_info.xml/fourteennm_sdm_jtagblock_info.xml/fourteennm_sdm_key_in_info.xml/fourteennm_sdm_loanio_info.xml/fourteennm_sdm_mbox_int_info.xml/fourteennm_sdm_nsp_info.xml/fourteennm_sdm_oscillator_info.xml/fourteennm_sdm_por_info.xml/fourteennm_sdm_pwr_alert_info.xml/fourteennm_sdm_tamper_info.xml/fourteennm_sdm_vsblock_info.xml/fourteennm_termination_info.xml/fourteennm_termination_logic_info.xml/fourteennm_tile_ctrl_info.xml/fourteennm_ufi_esram_info.xml/fourteennm_ufi_uib_info.xml/fourteennm_ufind4h_uib_info.xml/fourteennm_uib_io_phy_info.xml/fourteennm_uibssm_info.xml/global_mfam_info.xml/lpm_abs_info.xml/lpm_add_sub_info.xml/lpm_add_sub_rules.xml/lpm_and_info.xml/lpm_bustri_info.xml/lpm_clshift_info.xml/lpm_clshift_rules.xml/lpm_compare_info.xml/lpm_compare_rules.xml/lpm_constant_info.xml/lpm_counter_info.xml/lpm_decode_info.xml/lpm_divide_info.xml/lpm_ff_info.xml/lpm_inv_info.xml/lpm_latch_info.xml/lpm_mult_info.xml/lpm_mult_rules.xml/lpm_mux_info.xml/lpm_or_info.xml/lpm_ram_dp_info.xml/lpm_ram_dq_info.xml/lpm_ram_dq_rules.xml/lpm_ram_io_info.xml/lpm_rom_info.xml/lpm_shiftreg_info.xml/lpm_xor_info.xml/maxii_io_info.xml/maxii_jtag_info.xml/maxii_lcell_info.xml/maxii_ufm_info.xml/maxv_io_info.xml/maxv_jtag_info.xml/maxv_lcell_info.xml/maxv_ufm_info.xml/mfam_family_macros.xml/nadder_te_test_atom_info.xml/parallel_add_info.xml/parallel_add_rules.xml/reg_autovec_common_rules.xml/scfifo_info.xml/scfifo_rules.xml/scfifo_wiz_map.xml/sld_mod_ram_rom_info.xml/sld_virtual_jtag_basic_info.xml/sld_virtual_jtag_info.xml/stratix_crcblock_info.xml/stratix_dll_info.xml/stratix_io_info.xml/stratix_jtag_info.xml/stratix_lcell_info.xml/stratix_lvds_receiver_info.xml/stratix_lvds_transmitter_info.xml/stratix_mac_mult_info.xml/stratix_mac_out_info.xml/stratix_pll_info.xml/stratix_ram_block_info.xml/stratix_rublock_info.xml/stratixgx_crcblock_info.xml/stratixgx_dll_info.xml/stratixgx_io_info.xml/stratixgx_jtag_info.xml/stratixgx_lcell_info.xml/stratixgx_lvds_receiver_info.xml/stratixgx_lvds_transmitter_info.xml/stratixgx_mac_mult_info.xml/stratixgx_mac_out_info.xml/stratixgx_pll_info.xml/stratixgx_ram_block_info.xml/stratixgx_rublock_info.xml/stratixii_asmiblock_info.xml/stratixii_clkctrl_info.xml/stratixii_crcblock_info.xml/stratixii_dll_info.xml/stratixii_io_info.xml/stratixii_jtag_info.xml/stratixii_lcell_comb_info.xml/stratixii_lcell_ff_info.xml/stratixii_lvds_receiver_info.xml/stratixii_lvds_transmitter_info.xml/stratixii_mac_mult_info.xml/stratixii_mac_out_info.xml/stratixii_pll_info.xml/stratixii_ram_block_info.xml/stratixii_rublock_info.xml/stratixii_termination_info.xml/stratixiigx_asmiblock_info.xml/stratixiigx_clkctrl_info.xml/stratixiigx_crcblock_info.xml/stratixiigx_dll_info.xml/stratixiigx_io_info.xml/stratixiigx_jtag_info.xml/stratixiigx_lcell_comb_info.xml/stratixiigx_lcell_ff_info.xml/stratixiigx_lvds_receiver_info.xml/stratixiigx_lvds_transmitter_info.xml/stratixiigx_mac_mult_info.xml/stratixiigx_mac_out_info.xml/stratixiigx_pll_info.xml/stratixiigx_ram_block_info.xml/stratixiigx_rublock_info.xml/stratixiigx_termination_info.xml/stratixiii_asmiblock_info.xml/stratixiii_bias_block_info.xml/stratixiii_clkena_info.xml/stratixiii_clkselect_info.xml/stratixiii_crcblock_info.xml/stratixiii_ddio_in_info.xml/stratixiii_ddio_oe_info.xml/stratixiii_ddio_out_info.xml/stratixiii_delay_chain_info.xml/stratixiii_dll_info.xml/stratixiii_dll_offset_ctrl_info.xml/stratixiii_dqs_config_info.xml/stratixiii_dqs_delay_chain_info.xml/stratixiii_dqs_enable_ctrl_info.xml/stratixiii_dqs_enable_info.xml/stratixiii_ff_info.xml/stratixiii_half_rate_input_info.xml/stratixiii_input_phase_alignment_info.xml/stratixiii_io_clock_divider_info.xml/stratixiii_io_config_info.xml/stratixiii_io_ibuf_info.xml/stratixiii_io_obuf_info.xml/stratixiii_io_pad_info.xml/stratixiii_jtag_info.xml/stratixiii_lcell_comb_info.xml/stratixiii_lvds_receiver_info.xml/stratixiii_lvds_transmitter_info.xml/stratixiii_mac_mult_info.xml/stratixiii_mac_out_info.xml/stratixiii_mlab_cell_info.xml/stratixiii_otp_info.xml/stratixiii_output_phase_alignment_info.xml/stratixiii_pll_info.xml/stratixiii_pseudo_diff_out_info.xml/stratixiii_ram_block_info.xml/stratixiii_rublock_info.xml/stratixiii_termination_info.xml/stratixiii_termination_logic_info.xml/stratixiii_tsdblock_info.xml/stratixiv_asmiblock_info.xml/stratixiv_bias_block_info.xml/stratixiv_clkena_info.xml/stratixiv_clkselect_info.xml/stratixiv_crcblock_info.xml/stratixiv_ddio_in_info.xml/stratixiv_ddio_oe_info.xml/stratixiv_ddio_out_info.xml/stratixiv_delay_chain_info.xml/stratixiv_dll_info.xml/stratixiv_dll_offset_ctrl_info.xml/stratixiv_dqs_config_info.xml/stratixiv_dqs_delay_chain_info.xml/stratixiv_dqs_enable_ctrl_info.xml/stratixiv_dqs_enable_info.xml/stratixiv_ff_info.xml/stratixiv_half_rate_input_info.xml/stratixiv_input_phase_alignment_info.xml/stratixiv_io_clock_divider_info.xml/stratixiv_io_config_info.xml/stratixiv_io_ibuf_info.xml/stratixiv_io_obuf_info.xml/stratixiv_io_pad_info.xml/stratixiv_jtag_info.xml/stratixiv_lcell_comb_info.xml/stratixiv_lvds_receiver_info.xml/stratixiv_lvds_transmitter_info.xml/stratixiv_mac_mult_info.xml/stratixiv_mac_out_info.xml/stratixiv_mlab_cell_info.xml/stratixiv_otp_info.xml/stratixiv_output_phase_alignment_info.xml/stratixiv_pll_info.xml/stratixiv_pseudo_diff_out_info.xml/stratixiv_ram_block_info.xml/stratixiv_rublock_info.xml/stratixiv_termination_info.xml/stratixiv_termination_logic_info.xml/stratixiv_tsdblock_info.xml/stratixv_asmiblock_info.xml/stratixv_att_cdr_pll_info.xml/stratixv_atx_pll_info.xml/stratixv_bias_block_info.xml/stratixv_channel_pll_info.xml/stratixv_chipidblock_info.xml/stratixv_clk_phase_select_info.xml/stratixv_clkburst_info.xml/stratixv_clkena_info.xml/stratixv_clkselect_info.xml/stratixv_controller_info.xml/stratixv_crcblock_info.xml/stratixv_cvpcieblock_info.xml/stratixv_ddio_in_info.xml/stratixv_ddio_oe_info.xml/stratixv_ddio_out_info.xml/stratixv_delay_chain_info.xml/stratixv_dftblock_info.xml/stratixv_dll_info.xml/stratixv_dll_offset_ctrl_info.xml/stratixv_dqs_config_info.xml/stratixv_dqs_delay_chain_info.xml/stratixv_dqs_enable_ctrl_info.xml/stratixv_duty_cycle_adjustment_info.xml/stratixv_ff_info.xml/stratixv_fractional_pll_info.xml/stratixv_half_rate_input_info.xml/stratixv_input_phase_alignment_info.xml/stratixv_io_clock_divider_info.xml/stratixv_io_config_info.xml/stratixv_io_ibuf_info.xml/stratixv_io_obuf_info.xml/stratixv_io_pad_info.xml/stratixv_jtag_info.xml/stratixv_lcell_comb_info.xml/stratixv_leveling_delay_chain_info.xml/stratixv_lvds_rx_info.xml/stratixv_lvds_tx_info.xml/stratixv_mac_info.xml/stratixv_mlab_cell_info.xml/stratixv_opregblock_info.xml/stratixv_oscillator_info.xml/stratixv_output_alignment_info.xml/stratixv_phb_info.xml/stratixv_phy_clkbuf_info.xml/stratixv_pll_dll_output_info.xml/stratixv_pll_dpa_output_info.xml/stratixv_pll_extclk_output_info.xml/stratixv_pll_lvds_output_info.xml/stratixv_pll_output_counter_info.xml/stratixv_pll_reconfig_info.xml/stratixv_pll_refclk_select_info.xml/stratixv_prblock_info.xml/stratixv_pseudo_diff_out_info.xml/stratixv_ram_block_info.xml/stratixv_read_fifo_info.xml/stratixv_read_fifo_read_enable_info.xml/stratixv_rublock_info.xml/stratixv_termination_info.xml/stratixv_termination_logic_info.xml/stratixv_tsdblock_info.xml/tennm_clk_burst_info.xml/tennm_clk_divider_info.xml/tennm_clk_gate_info.xml/tennm_clk_select_info.xml/tennm_cpa_info.xml/tennm_ddio_in_info.xml/tennm_ddio_oe_info.xml/tennm_ddio_out_info.xml/tennm_esram_info.xml/tennm_ff_info.xml/tennm_fp_mac_info.xml/tennm_hbmc_info.xml/tennm_hps_hps_info.xml/tennm_hps_mpfe_info.xml/tennm_io48_phyclk_info.xml/tennm_io_12_lane_info.xml/tennm_io_ibuf_info.xml/tennm_io_obuf_info.xml/tennm_io_pad_info.xml/tennm_io_serdes_dpa_info.xml/tennm_iopll_info.xml/tennm_iossm_info.xml/tennm_lcell_comb_info.xml/tennm_logic_module_info.xml/tennm_logical_pll_info.xml/tennm_lsm_avmm_master_info.xml/tennm_lsm_avmm_slave_info.xml/tennm_lsm_bf_info.xml/tennm_lsm_gpio_in_info.xml/tennm_lsm_gpio_intr_info.xml/tennm_lsm_gpio_out_info.xml/tennm_lsm_soft_logic_reset_info.xml/tennm_mac_info.xml/tennm_mlab_cell_info.xml/tennm_pseudo_diff_out_info.xml/tennm_ram_block_info.xml/tennm_refclk_input_info.xml/tennm_sdm_axi_fpga2sdm_info.xml/tennm_sdm_axi_sdm2fpga_info.xml/tennm_sdm_fpga_core_rst_info.xml/tennm_sdm_gpio_in_info.xml/tennm_sdm_gpio_intr_info.xml/tennm_sdm_gpio_intr_out_info.xml/tennm_sdm_gpio_out_info.xml/tennm_sdm_jtag_ela_info.xml/tennm_sdm_jtag_mon_info.xml/tennm_sdm_jtagblock_info.xml/tennm_sdm_loanio_info.xml/tennm_sdm_mbox_int_info.xml/tennm_sdm_oscillator_info.xml/tennm_sdm_por_info.xml/tennm_sdm_pwr_alert_info.xml/tennm_sdm_tamper_info.xml/tennm_termination_info.xml/tennm_tile_ctrl_info.xml/tennm_ufi_info.xml/tennm_ufi_uib_info.xml/te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filenames: src_hdl
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filenames: inc/src
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filenames: csrgen_output
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filenames:
[cell repeats an earlier one in this file: 100 characters]


filenames: alt_vip_common_event_packet_decode.sv
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filenames:
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filenames: data_sink_util.h
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filetypes: ffffd
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filenames:
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filenames: inc/src
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filenames: alt_aeu_100_pfc_top.v
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filenames: msim_wave.do/msim_wave_pr.do/tb_run.tcl
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filenames: aldec/alt_vip_packet_duplicator_hw.tcl/cadence/mentor/src_hdl/synopsys
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filenames: intel_mbox_reset_handler.sv/intel_mbox_reset_handler_hw.tcl
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filenames:
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filenames:
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filenames: ctype_base.h/ctype_configure_char.cc/ctype_inline.h/error_constants.h/os_defines.h
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filenames:
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filenames: C.pl/D.pl/R.pl/T.pl/U.pl
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filenames: functional/memory
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filenames: altera_external_memory_bfm.sv/altera_external_memory_bfm_vhdl_wrapper.sv
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dirname:
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filenames: afu_id_avmm_slave/magic_number_rom
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dirname:
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filenames: altera_mm_mgmt_wrapper.sv/altera_mm_mgmt_wrapper_hw.tcl
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dirname:
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filenames:
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filenames: src_hdl
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filenames:
[cell repeats an earlier one in this file: 129 characters]


filenames: run.tcl/test.sv
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dirname:
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filenames: intel_pcie_bas.sv
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dirname:
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filetypes: fffffffffffffffffffffffffff
dirname:
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filenames:
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filenames: src_hdl
filetypes: d
dirname:
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filenames: altera_eth_xgmii_ptp_inserter.v
filetypes: f
dirname:
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dirname: /opt/intel/oneapi/intelfpgadpcpp/2021.1.1/QuartusPrimePro/19.2/quartus/common/devinfo/20nm
filenames:
  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