# filelist

filenames: altera_up_avalon_video_dual_clock_buffer_hw.tcl/hdl
filetypes: fd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/university_program/audio_video/video/altera_up_avalon_video_dual_clock_buffer


filetypes: fffffffffffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/altera_hdmi/src/hdmi_2.x/rx/mentor/frl

filenames:
[cell repeats an earlier one in this file: 557 characters]


filetypes: fffffffffffffffffffffffffffffffffffffffffffffffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/intel_rtile/common/rtl/spyglass/csb_adaptor

filenames:
  intel_rtile_apperr2csb.sv/intel_rtile_avmm2csb.sv/intel_rtile_com_mcsb.sv/intel_rtile_com_tcsb.sv/intel_rtile_csb2cii.sv/intel_rtile_csb2cplto.sv/intel_rtile_csb2pcicfg.sv/intel_rtile_csb_adaptor.sv/intel_rtile_csbcgcgu.sv/intel_rtile_csbcism.sv/intel_rtile_csbcport.sv/intel_rtile_csbebase.sv/intel_rtile_csbendpoint.sv/intel_rtile_csbep_wrapper.sv/intel_rtile_cxl_csb2aermsg.sv/intel_rtile_cxl_csb2cfgupdate.sv/intel_rtile_cxl_csb2hiperr.sv/intel_rtile_cxl_pm2csb.sv/intel_rtile_flr2csb.sv/intel_rtile_pcie_csb2serr.sv/intel_rtile_pcie_csb2vferr.sv/intel_rtile_pcie_int2csb.sv/intel_rtile_pcie_pm2csb.sv/intel_rtile_pcie_prs2csb.sv/intel_rtile_pcie_vw2csb.sv/intel_rtile_pulsesync.sv/rnr_com_syncfifo.sv/rnr_csb_cfgif.sv/rnr_csb_common_module.sv/rnr_csb_pkg.sv/rnr_csbcasyncclkreq.sv/rnr_csbcasyncfifo.sv/rnr_csbcasyncfifo_egr.sv/rnr_csbcasyncfifo_ing.sv/rnr_csbccomp.sv/rnr_csbcegress.sv/rnr_csbcfifo.sv/rnr_csbcingress.sv/rnr_csbcinqueue.sv/rnr_csbcusync_clk1.sv/rnr_csbcusync_clk2.sv/rnr_csbebulkrdwr.sv/rnr_csbebulkrdwrwrapper.sv/rnr_csbebytecount.sv/rnr_csbedoserrmstr.sv/rnr_csbehierinsert.sv/rnr_csbemstr.sv/rnr_csbemstrreg.sv/rnr_csbetregsplitter.sv/rnr_csbetrgt.sv/rnr_csbetrgtreg.sv/rnr_divclk.sv/rnr_mux2.sv


filenames: address_decoder_top_altera_merlin_slave_agent_191_ncfkfri.sv/altera_merlin_burst_uncompressor.sv
filetypes: ff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/ethernet/altera_eth_tse/example_project/common/hw_design/address_decoder/address_decoder_top/altera_merlin_slave_agent


filenames: intel_generic_serial_flash_interface_top_regs.h
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/pgm/intel_generic_serial_flash_interface/intel_generic_serial_flash_interface_top/inc


filenames: design_example_rules/pkgIndex.tcl/presets/tcl/terp
filetypes: dfddd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_s20_htile


filenames: cm_rule_cpri_auto.tcl/cm_rule_cpri_auto_tb.tcl
filetypes: ff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_s10_common_design_example_rules/cm_rule_cpri_auto


filetypes: fffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/alt_interlaken/altera_interlaken_hsio_bank/altera_interlaken_hsio_bank_bpcs_3g

filenames:
[cell repeats an earlier one in this file: 160 characters]


filenames: alt_ehipc2_lut6.v
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/ethernet/alt_ehipc2/synopsys/rtl/alt_ehipc2_lib/hslx/fm


filenames: mcgb.tcl
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/alt_xcvr/altera_xcvr_pll/mcgb_package_s20/tcl


filenames: mentor/synopsys/xcelium
filetypes: ddd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/dynamic_reconfiguration/etile_dynamic_reconfiguration/example_design/ETH25G_PTP_RSFEC/example_testbench/s10


filenames: tb_run.sh/tb_top.ucli.txt
filetypes: ff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/ethernet/alt_em10g32/example_design/LL10G_10GBASER_RegMode/simulation/ed_sim/synopsys/vcs


filenames: ast/csr/efc/mac/pcs/top
filetypes: dddddd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/ethernet/alt_e40emu/40g/synopsys/rtl


filetypes: ffffffffffffffffffffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/iconnect/alt_hiconnect_dc_fifo

filenames:
[cell repeats an earlier one in this file: 615 characters]


filetypes: fffffffffffffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/alt_eth_40g_100g/40gbe/rtl_src/phy/mentor/pcs/rx

filenames:
[cell repeats an earlier one in this file: 459 characters]


filenames: alt_vip_vfb_wr_ctrl.ocp/alt_vip_vfb_wr_ctrl.sv
filetypes: ff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/vip/ip_library/component_ip/utility/alt_vip_vfb_wr_ctrl/src_hdl


filenames: alt_vip_common_sync.v
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/vip/ip_library/common_hdl/modules/alt_vip_common_sync/src_hdl


filenames: altera_voltage_sensor_control.sv/voltage_sensor_avalon_control.sv/voltage_sensor_wrapper.sv
filetypes: fff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/altera_voltage_sensor/control/cadence


filenames: intel_hdmi_rx_core_phy_intf.v/intel_hdmi_rx_oversample.v
filetypes: ff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/altera_hdmi/src/phy_intf/rx/aldec


filetypes: dffffffffffffffffffffffdf
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/altera_pcie/altera_pcie_a10_hip/aldec

filenames:
  a10_hip_ast_translator/altpcie_a10_gbfifo.v/altpcie_a10_hip_hwtcl_noterp_check.v/altpcie_a10_lmi_burst_intf.v/altpcie_a10_scfifo_ext.v/altpcie_monitor_a10_dlhip_sim.sv/altpcie_reset_delay_sync.v/altpcie_rs_a10_hip.v/altpcie_rs_a10_serdes.v/altpcie_sc_bitsync.v/altpcie_sc_ctrl.v/altpcie_sc_dprio_rd_wr.v/altpcie_sc_dprio_seq.v/altpcie_sc_dprio_top.v/altpcie_sc_hip_vecsync2.v/altpcie_sc_lvlsync.v/altpcie_sc_lvlsync2.v/altpcie_scfifo_a10.v/altpcie_tlp_inspector_a10.v/altpcie_tlp_inspector_cseb_a10.sv/altpcie_tlp_inspector_monitor_a10.sv/altpcie_tlp_inspector_pcsig_drive_a10.v/altpcie_tlp_inspector_trigger_a10.v/rp_avmm_256/skp_det_g3.v


filenames: main.tcl/reg_map_inc.tcl
filetypes: ff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/ethernet/alt_e40c3/example_project/hwtest/altera/sval_top


filetypes: ffffffffffffffffffffffffffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/ethernet/alt_ehipc3_fm/example_project/common/alt_ehipc3_fm_sl_traffic_controller

filenames:
[cell repeats an earlier one in this file: 645 characters]


filenames: alt_e40_block_distributor.v/alt_e40_pcs.v/alt_e40_pcs_rx.v/alt_e40_pcs_tx.v
filetypes: ffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/ethernet/alt_e40/40g/rtl/cadence/pcs


filenames: altera_eth_link_fault_generation.v
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/ethernet/ethernet_ucore/altera_eth_link_fault_generation/cadence


filetypes: ffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/vip/ip_library/component_ip/processing/alt_vip_cps_alg_core/cadence/src_hdl

filenames:
[cell repeats an earlier one in this file: 118 characters]


filenames: src_hdl
filetypes: d
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/vip/ip_library/component_ip/processing/alt_vip_scaler_alg_core/cadence


filenames: Accelerometer_SPI_Mode.pdf
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/university_program/input_output/altera_up_avalon_accelerometer_spi/doc


filenames: mgc.pkginfo/mgcld/mgls_asynch
filetypes: fff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/mentor_vip_ae/common/linux/mgls/lib


filetypes: fffffffffffffffffffffffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/alt_xcvr/altera_xcvr_10gbase_kr/gige_pcs/aldec

filenames:
[cell repeats an earlier one in this file: 849 characters]


filenames: pkgIndex.tcl/source/tcl
filetypes: fdd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/alt_xcvr/altera_xcvr_pll/altera_xcvr_cdr_pll_s20


filetypes: fffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/ethernet/alt_e100s10/100g/mentor/rtl/efc

filenames:
[cell repeats an earlier one in this file: 238 characters]


filenames: alt_vip_common_message_pipeline_stage.sv
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/vip/ip_library/common_hdl/aldec/modules/alt_vip_common_message_pipeline_stage/src_hdl


filenames: src_hdl
filetypes: d
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/vip/ip_library/component_ip/processing/alt_vip_dil_low_angle_algorithm/synopsys


filetypes: dfdddddddddd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/altera_pcie/altera_pcie_s10_hip_avmm_bridge/mentor

filenames:
[cell repeats an earlier one in this file: 298 characters]


filetypes: dfddfffffffffffffffffffffffffffd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/ethernet/alt_eth_ultra/100g_bm_vhd

filenames:
[cell repeats an earlier one in this file: 521 characters]


filenames: src_hdl
filetypes: d
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/vip/ip_library/component_ip/schedulers/alt_vip_scaler_scheduler/aldec


filenames: altpcie_a10_hip_ast_translator.sv/altpcie_ast_translator.sv
filetypes: ff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/altera_pcie/altera_pcie_a10_hip/synopsys/a10_hip_ast_translator


filetypes: fffffffffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/altera_hdmi/src/hdmi_2.x/tx/cadence/frl

filenames:
[cell repeats an earlier one in this file: 470 characters]


filetypes: ddddd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/vvp/component_library/tcl_components/imported/warp

filenames:
  intel_vvp_warp_b2r/intel_vvp_warp_engine/intel_vvp_warp_mem_ctrl/intel_vvp_warp_r2b/intel_vvp_warp_top


filenames: altera_eth_xgmii_tsu.v
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/ethernet/ethernet_ucore/altera_eth_xgmii_tsu/mentor


filenames: altpciexpav_lite_app.v
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/altera_pcie/altera_pcie_av_hip_avmm/synopsys/avalon_lite


filenames: src_hdl
filetypes: d
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/vip/ip_library/component_ip/utility/alt_vip_pip_sop_realign/synopsys


filetypes: dfdfdffddd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/ethernet/alt_em10g32/example_design/LL10G_10G_USXGMII_1588v2/hwtesting/system_console

filenames:
[cell repeats an earlier one in this file: 124 characters]


filenames: alt_vip_common_mult_add_nodsp.sv
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/vip/ip_library/common_hdl/synopsys/modules/alt_vip_common_mult_add_nodsp/src_hdl


filenames: mentor_vip_ae_rh.pdf/mentor_vip_ae_rn.pdf
filetypes: ff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/mentor_vip_ae/release_documents


filenames: altera_xcvr_native_a10_hw.tcl/fileset.tcl/interfaces.tcl/module.tcl/parameters.tcl
filetypes: fffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_vi/tcl


filenames: alt_vip_packet_duplicator.sv
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/vip/ip_library/component_ip/utility/alt_vip_packet_duplicator/synopsys/src_hdl


filenames: Makefile.txt/mcdma-driver/mqdma-driver
filetypes: fdd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/intel_pcie/mcdma/software/kernel/driver/kmod


filenames: address_decoder_multi_channel_altera_mm_interconnect_1920_luq3imy.v
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/ethernet/altera_eth_tse/example_project/common/hw_design/address_decoder/address_decoder_multi_channel/altera_mm_interconnect


filetypes: ffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/ethernet/alt_e25s10/25g/cadence/rtl/csr

filenames:
[cell repeats an earlier one in this file: 291 characters]


filetypes: ffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/sld/jtag/altera_sld_jtag_bridge_host

filenames:
[cell repeats an earlier one in this file: 142 characters]


filenames: altera_eth_tse_avalon_arbiter.v
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/ethernet/tse_ucores/altera_eth_tse_avalon_arbiter/aldec


filenames: altera_emif_local_reset_combiner.sdc
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/emif/ip_local_reset_combiner/timing


filenames: fp_add_a10.vhd/fp_add_s10.vhd/fp_mult_a10.vhd/fp_mult_s10.vhd
filetypes: ffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/dsp/altera_fft_ii/mentor/src/rtl/lib/r22sdf/hdfp


filenames: intel_vvp_ext_to_int_scheduler.sv
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/vvp/component_library/tcl_components/schedulers/intel_vvp_ext_to_int_scheduler/synopsys/src_hdl


filetypes: ddffddd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/vvp/component_library/tcl_components/imported/warp/intel_vvp_warp_mem_ctrl

filenames:
  aldec/cadence/intel_vvp_warp_mem_ctrl_core_hw.tcl/intel_vvp_warp_mem_ctrl_hw.tcl/mentor/src_hdl/synopsys


filenames: tb_run.sh/tb_top.ucli.txt/vcs_wave.tcl
filetypes: fff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/ethernet/alt_em10g32/example_design/LL10G_LINESIDE/simulation/ed_sim/synopsys/vcs


filenames: common/rx/tx
filetypes: ddd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/altera_dp/src/synopsys/bitec_dp


filenames: inc/license-ucosii.txt/src
filetypes: dfd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/nios2_ip/altera_nios2_gen2/UCOSII


filetypes: fffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/ethernet/alt_eth_ultra/100g/rtl/eth

filenames:
[cell repeats an earlier one in this file: 107 characters]


filetypes: fffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/altera_pcie/altera_pcie_sriov/cadence/bench

filenames:
[cell repeats an earlier one in this file: 125 characters]


filenames: altera_reset_controller.v/altera_reset_synchronizer.v
filetypes: ff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/merlin/altera_reset_controller/synopsys


filetypes: ffffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/altera_jesd204/src/tx/s10_16g/aldec

filenames:
[cell repeats an earlier one in this file: 285 characters]


filetypes: ffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/merlin/altera_avalon_mm_cci_bridge

filenames:
[cell repeats an earlier one in this file: 136 characters]


filetypes: ffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/altera_pcie/altera_pcie_s10_hip_avmm_bridge/cadence/altera_pcie_s10_hptxs

filenames:
[cell repeats an earlier one in this file: 172 characters]


filenames: src_hdl
filetypes: d
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/vip/ip_library/component_ip/processing/alt_vip_crs_h_down_core/mentor


filenames: tod_inc.tcl/tod_reg_map.tcl
filetypes: ff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/ethernet/alt_em10g32/example_design/LL10G_LINESIDE_1588v2/hwtesting/system_console/tod


filenames: alt_interlaken_4lane_3g_tb.sv/run_simulation.do
filetypes: ff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/alt_interlaken/design_examples/alt_interlaken_4lane_3g/testbench


filetypes: fffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/intel_pcie/avmm_bridge_1024_ed/mentor/intel_pcie_bam_v2

filenames:
[cell repeats an earlier one in this file: 246 characters]


filenames: alt_vip_common_fifo.v
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/vip/ip_library/common_hdl/synopsys/modules/alt_vip_common_fifo/src_hdl


filenames: src_hdl
filetypes: d
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/vvp/component_library/tcl_components/utility/intel_vvp_slave_data_split/cadence


filenames: alt_e100_phy_pcs.v/alt_e100_phy_pcs_caui4.v/common/rx/tx
filetypes: ffddd
dirname:
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filetypes: fffff
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filetypes: dffffddd
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filenames: avalonstloopback/gen/mon/traffic_controller.tcl
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filenames: altera_phylite_s20_cfg_ctrl.sv
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filenames: src_hdl
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filenames: harq_combine.v/harq_ddr_adapter.sv/harq_fifo.sv/harq_top.v
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filetypes: fffffffffffffffffffffffffffffffffffff
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filenames: src_hdl
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filenames:
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filenames: alt_vip_cvo_scheduler.ocp/alt_vip_cvo_scheduler.sv
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filetypes: fffffff
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filetypes: fffffff
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dirname:
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filenames:
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filenames: hyper_opt_OFF_pkg.vhd/hyper_opt_ON_pkg.vhd
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filenames:
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filenames: ilk_12l_10g_rx_stripe_adapter.v/ilk_12l_10g_tx_stripe_adapter.v
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dirname:
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filenames:
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filetypes: fffffffffffffff
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filenames:
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filetypes: ffffffff
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filenames:
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filenames: alt_e40_fec_valid_gen.v/alt_e40_seq_reco_n.v/common_src/sv_fec
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dirname:
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filenames: altera_pcie_s10_rxm.sv
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dirname:
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filenames: src_hdl
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dirname:
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filenames: j204c_tx_regmap.v
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dirname:
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filenames:
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filenames: altera_external_memory_bfm.sv/altera_external_memory_bfm_vhdl_wrapper.sv
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dirname:
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filenames: alt_hiconnect_av_mstr_trans.sv/alt_hiconnect_av_mstr_trans_hw.tcl
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dirname:
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dirname:
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filenames: altera_connection_identification_hub.sv.terp/altera_connection_identification_hub_hw.tcl
filetypes: ff
dirname:
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filenames: src_hdl
filetypes: d
dirname:
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filetypes: dfffffddd
dirname:
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filenames:
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filenames: src_hdl
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dirname:
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filetypes: dffffddd
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filenames:
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filenames: alt_e40_fc_top.v/alt_e40_rx_fc.v/alt_e40_tx_fc.v/alt_e40_tx_fc_frame_muxer.v
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dirname:
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filenames: alt_vip_message_sink_terminator.sv
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dirname:
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filenames: src_hdl
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dirname:
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filenames: src_hdl
filetypes: d
dirname:
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filetypes: fffffffffffffffffffffffffffffffffffffffffffffffffff
dirname:
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filenames:
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filetypes: ffffffff
dirname:
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filenames:
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filetypes: ffffffffffffffff
dirname:
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filenames:
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filenames: ncsim_wave.tcl/tb_run.sh
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dirname:
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filenames: altera_eth_link_fault_generation_unidirectional.v
filetypes: f
dirname:
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filenames: ncsim_wave.svwf.txt/ncsim_wave.tcl/tb_run.sh
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dirname:
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filenames: intel_pcie_bas.sv/intel_pcie_lite_bas.sv
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dirname:
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filetypes: fffffffff
dirname:
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filenames:
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filenames: intel_pcie_cs.sv/intel_pcie_cs_parser.sv
filetypes: ff
dirname:
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filenames: altera_eth_tse_regs.h
filetypes: f
dirname:
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filenames: ncsim_wave.tcl/tb_run.sh
filetypes: ff
dirname:
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filetypes: fffffff
dirname:
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filenames:
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filetypes: fffffffff
dirname:
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filenames:
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filenames: gen/mon/package
filetypes: ddd
dirname:
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filetypes: fffffff
dirname:
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filenames:
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filenames: alt_a10mlab.v/alt_wys_lut.v
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dirname:
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filenames: alt_vip_csc_alg_core.sv
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dirname:
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filetypes: dfffddd
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filenames:
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filenames: aldec/altera_eth_default_slave.v/altera_eth_default_slave_hw.tcl/cadence/mentor/synopsys
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dirname:
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filetypes: dddddd
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filenames:
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filenames: aldec/altera_emif_ddrt_i2c_mux.v/altera_emif_ddrt_i2c_mux_hw.tcl/cadence/mentor/spyglass/synopsys
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dirname:
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filenames:
  avr_hssi_common_util.tcl/avr_hssi_parameters.tcl/ct1_atx_pll_avmm2_if_rbc.tcl/ct1_atx_pll_avmm2_if_simple.tcl/ct1_atx_pll_param_mapping_util.tcl/ct1_atx_pll_parameters.tcl/ct1_atx_pll_rbc.tcl/ct1_atx_pll_simple.tcl/ct1_atx_pll_util.tcl/ct1_cdr_pll_parameters.tcl/ct1_cdr_pll_rbc.tcl/ct1_cdr_pll_simple.tcl/ct1_cmu_fpll_param_mapping_util.tcl/ct1_cmu_fpll_parameters.tcl/ct1_cmu_fpll_rbc.tcl/ct1_cmu_fpll_refclk_select_mux_rbc.tcl/ct1_cmu_fpll_simple.tcl/ct1_cmu_fpll_util.tcl/ct1_fpll_avmm2_if_rbc.tcl/ct1_fpll_avmm2_if_simple.tcl/ct1_hssi_10g_rx_pcs_rbc.tcl/ct1_hssi_10g_rx_pcs_simple.tcl/ct1_hssi_10g_tx_pcs_rbc.tcl/ct1_hssi_10g_tx_pcs_simple.tcl/ct1_hssi_8g_rx_pcs_rbc.tcl/ct1_hssi_8g_rx_pcs_simple.tcl/ct1_hssi_8g_tx_pcs_rbc.tcl/ct1_hssi_8g_tx_pcs_simple.tcl/ct1_hssi_adapt_rx_rbc.tcl/ct1_hssi_adapt_rx_simple.tcl/ct1_hssi_adapt_tx_rbc.tcl/ct1_hssi_adapt_tx_simple.tcl/ct1_hssi_aibcr_rx_rbc.tcl/ct1_hssi_aibcr_rx_simple.tcl/ct1_hssi_aibcr_tx_rbc.tcl/ct1_hssi_aibcr_tx_simple.tcl/ct1_hssi_aibnd_rx_rbc.tcl/ct1_hssi_aibnd_rx_simple.tcl/ct1_hssi_aibnd_tx_rbc.tcl/ct1_hssi_aibnd_tx_simple.tcl/ct1_hssi_avmm1_if_rbc.tcl/ct1_hssi_avmm1_if_simple.tcl/ct1_hssi_common_pcs_pma_interface_rbc.tcl/ct1_hssi_common_pcs_pma_interface_simple.tcl/ct1_hssi_common_pld_pcs_interface_rbc.tcl/ct1_hssi_common_pld_pcs_interface_simple.tcl/ct1_hssi_common_util.tcl/ct1_hssi_fifo_rx_pcs_rbc.tcl/ct1_hssi_fifo_rx_pcs_simple.tcl/ct1_hssi_fifo_tx_pcs_rbc.tcl/ct1_hssi_fifo_tx_pcs_simple.tcl/ct1_hssi_gen3_rx_pcs_rbc.tcl/ct1_hssi_gen3_rx_pcs_simple.tcl/ct1_hssi_gen3_tx_pcs_rbc.tcl/ct1_hssi_gen3_tx_pcs_simple.tcl/ct1_hssi_krfec_rx_pcs_rbc.tcl/ct1_hssi_krfec_rx_pcs_simple.tcl/ct1_hssi_krfec_tx_pcs_rbc.tcl/ct1_hssi_krfec_tx_pcs_simple.tcl/ct1_hssi_param_mapping_util.tcl/ct1_hssi_parameters.tcl/ct1_hssi_pipe_gen1_2_rbc.tcl/ct1_hssi_pipe_gen1_2_simple.tcl/ct1_hssi_pipe_gen3_rbc.tcl/ct1_hssi_pipe_gen3_simple.tcl/ct1_hssi_pldadapt_rx_rbc.tcl/ct1_hssi_pldadapt_rx_simple.tcl/ct1_hssi_pldadapt_tx_rbc.tcl/ct1_hssi_pldadapt_tx_simple.tcl/ct1_hssi_pma_cgb_master_rbc.tcl/ct1_hssi_pma_lc_refclk_select_mux_rbc.tcl/ct1_hssi_refclk_divider_rbc.tcl/ct1_hssi_rx_pcs_pma_interface_rbc.tcl/ct1_hssi_rx_pcs_pma_interface_simple.tcl/ct1_hssi_rx_pld_pcs_interface_rbc.tcl/ct1_hssi_rx_pld_pcs_interface_simple.tcl/ct1_hssi_tx_pcs_pma_interface_rbc.tcl/ct1_hssi_tx_pcs_pma_interface_simple.tcl/ct1_hssi_tx_pld_pcs_interface_rbc.tcl/ct1_hssi_tx_pld_pcs_interface_simple.tcl/ct1_mcgb_parameters.tcl/ct1_mcgb_util.tcl/ct1_pma_adapt_rbc.tcl/ct1_pma_adapt_simple.tcl/ct1_pma_cdr_refclk_rbc.tcl/ct1_pma_cdr_refclk_simple.tcl/ct1_pma_cgb_rbc.tcl/ct1_pma_cgb_simple.tcl/ct1_pma_rx_buf_rbc.tcl/ct1_pma_rx_buf_simple.tcl/ct1_pma_rx_deser_rbc.tcl/ct1_pma_rx_deser_simple.tcl/ct1_pma_rx_dfe_rbc.tcl/ct1_pma_rx_dfe_simple.tcl/ct1_pma_rx_odi_rbc.tcl/ct1_pma_rx_odi_simple.tcl/ct1_pma_rx_sd_rbc.tcl/ct1_pma_rx_sd_simple.tcl/ct1_pma_tx_buf_rbc.tcl/ct1_pma_tx_buf_simple.tcl/ct1_pma_tx_ser_rbc.tcl/ct1_pma_tx_ser_simple.tcl/ct2_atx_pll_avmm2_if_rbc.tcl/ct2_atx_pll_avmm2_if_simple.tcl/ct2_atx_pll_param_mapping_util.tcl/ct2_atx_pll_parameters.tcl/ct2_atx_pll_rbc.tcl/ct2_atx_pll_simple.tcl/ct2_atx_pll_util.tcl/ct2_cdr_pll_parameters.tcl/ct2_cdr_pll_rbc.tcl/ct2_cdr_pll_simple.tcl/ct2_cmu_fpll_param_mapping_util.tcl/ct2_cmu_fpll_parameters.tcl/ct2_cmu_fpll_rbc.tcl/ct2_cmu_fpll_refclk_select_mux_rbc.tcl/ct2_cmu_fpll_simple.tcl/ct2_cmu_fpll_util.tcl/ct2_fpll_avmm2_if_rbc.tcl/ct2_fpll_avmm2_if_simple.tcl/ct2_hssi_10g_rx_pcs_rbc.tcl/ct2_hssi_10g_rx_pcs_simple.tcl/ct2_hssi_10g_tx_pcs_rbc.tcl/ct2_hssi_10g_tx_pcs_simple.tcl/ct2_hssi_8g_rx_pcs_rbc.tcl/ct2_hssi_8g_rx_pcs_simple.tcl/ct2_hssi_8g_tx_pcs_rbc.tcl/ct2_hssi_8g_tx_pcs_simple.tcl/ct2_hssi_adapt_rx_rbc.tcl/ct2_hssi_adapt_rx_simple.tcl/ct2_hssi_adapt_tx_rbc.tcl/ct2_hssi_adapt_tx_simple.tcl/ct2_hssi_aibcr_rx_rbc.tcl/ct2_hssi_aibcr_rx_simple.tcl/ct2_hssi_aibcr_tx_rbc.tcl/ct2_hssi_aibcr_tx_simple.tcl/ct2_hssi_aibnd_rx_rbc.tcl/ct2_hssi_aibnd_rx_simple.tcl/ct2_hssi_aibnd_tx_rbc.tcl/ct2_hssi_aibnd_tx_simple.tcl/ct2_hssi_avmm1_if_rbc.tcl/ct2_hssi_avmm1_if_simple.tcl/ct2_hssi_common_pcs_pma_interface_rbc.tcl/ct2_hssi_common_pcs_pma_interface_simple.tcl/ct2_hssi_common_pld_pcs_interface_rbc.tcl/ct2_hssi_common_pld_pcs_interface_simple.tcl/ct2_hssi_common_util.tcl/ct2_hssi_fifo_rx_pcs_rbc.tcl/ct2_hssi_fifo_rx_pcs_simple.tcl/ct2_hssi_fifo_tx_pcs_rbc.tcl/ct2_hssi_fifo_tx_pcs_simple.tcl/ct2_hssi_gen3_rx_pcs_rbc.tcl/ct2_hssi_gen3_rx_pcs_simple.tcl/ct2_hssi_gen3_tx_pcs_rbc.tcl/ct2_hssi_gen3_tx_pcs_simple.tcl/ct2_hssi_krfec_rx_pcs_rbc.tcl/ct2_hssi_krfec_rx_pcs_simple.tcl/ct2_hssi_krfec_tx_pcs_rbc.tcl/ct2_hssi_krfec_tx_pcs_simple.tcl/ct2_hssi_param_mapping_util.tcl/ct2_hssi_parameters.tcl/ct2_hssi_pipe_gen1_2_rbc.tcl/ct2_hssi_pipe_gen1_2_simple.tcl/ct2_hssi_pipe_gen3_rbc.tcl/ct2_hssi_pipe_gen3_simple.tcl/ct2_hssi_pldadapt_rx_rbc.tcl/ct2_hssi_pldadapt_rx_simple.tcl/ct2_hssi_pldadapt_tx_rbc.tcl/ct2_hssi_pldadapt_tx_simple.tcl/ct2_hssi_pma_cgb_master_rbc.tcl/ct2_hssi_pma_cgb_master_simple.tcl/ct2_hssi_pma_lc_refclk_select_mux_rbc.tcl/ct2_hssi_refclk_divider_rbc.tcl/ct2_hssi_rx_pcs_pma_interface_rbc.tcl/ct2_hssi_rx_pcs_pma_interface_simple.tcl/ct2_hssi_rx_pld_pcs_interface_rbc.tcl/ct2_hssi_rx_pld_pcs_interface_simple.tcl/ct2_hssi_tx_pcs_pma_interface_rbc.tcl/ct2_hssi_tx_pcs_pma_interface_simple.tcl/ct2_hssi_tx_pld_pcs_interface_rbc.tcl/ct2_hssi_tx_pld_pcs_interface_simple.tcl/ct2_mcgb_parameters.tcl/ct2_mcgb_util.tcl/ct2_pma_adapt_rbc.tcl/ct2_pma_adapt_sequencer_rbc.tcl/ct2_pma_adapt_sequencer_simple.tcl/ct2_pma_adapt_simple.tcl/ct2_pma_cdr_refclk_rbc.tcl/ct2_pma_cdr_refclk_simple.tcl/ct2_pma_cgb_rbc.tcl/ct2_pma_cgb_simple.tcl/ct2_pma_pcie_gen_switch_rbc.tcl/ct2_pma_reset_sequencer_rbc.tcl/ct2_pma_reset_sequencer_simple.tcl/ct2_pma_rx_buf_rbc.tcl/ct2_pma_rx_buf_simple.tcl/ct2_pma_rx_deser_rbc.tcl/ct2_pma_rx_deser_simple.tcl/ct2_pma_rx_dfe_rbc.tcl/ct2_pma_rx_dfe_simple.tcl/ct2_pma_rx_odi_rbc.tcl/ct2_pma_rx_odi_simple.tcl/ct2_pma_rx_sd_rbc.tcl/ct2_pma_rx_sd_simple.tcl/ct2_pma_tx_buf_rbc.tcl/ct2_pma_tx_buf_simple.tcl/ct2_pma_tx_sequencer_rbc.tcl/ct2_pma_tx_sequencer_simple.tcl/ct2_pma_tx_ser_rbc.tcl/ct2_pma_tx_ser_simple.tcl/ct2_pma_txpath_chnsequencer_rbc.tcl/ct2_pma_txpath_chnsequencer_simple.tcl/ct3_hssi_adapt_rx_rbc.tcl/ct3_hssi_adapt_rx_simple.tcl/ct3_hssi_adapt_tx_rbc.tcl/ct3_hssi_adapt_tx_simple.tcl/ct3_hssi_aibcr_rx_rbc.tcl/ct3_hssi_aibcr_rx_simple.tcl/ct3_hssi_aibcr_tx_rbc.tcl/ct3_hssi_aibcr_tx_simple.tcl/ct3_hssi_aibnd_rx_rbc.tcl/ct3_hssi_aibnd_rx_simple.tcl/ct3_hssi_aibnd_tx_rbc.tcl/ct3_hssi_aibnd_tx_simple.tcl/ct3_hssi_avmm1_if_rbc.tcl/ct3_hssi_avmm1_if_simple.tcl/ct3_hssi_avmm2_if_rbc.tcl/ct3_hssi_avmm2_if_simple.tcl/ct3_hssi_common_util.tcl/ct3_hssi_ehip_lane_rbc.tcl/ct3_hssi_ehip_lane_simple.tcl/ct3_hssi_param_mapping_util.tcl/ct3_hssi_parameters.tcl/ct3_hssi_pldadapt_rx_rbc.tcl/ct3_hssi_pldadapt_rx_simple.tcl/ct3_hssi_pldadapt_tx_rbc.tcl/ct3_hssi_pldadapt_tx_simple.tcl/ct3_hssi_rsfec_rbc.tcl/ct3_hssi_rsfec_simple.tcl/ct3_hssi_rsfecrx_mux_rbc.tcl/ct3_hssi_rsfecrx_mux_simple.tcl/ct3_hssi_xcvr_rbc.tcl/ct3_hssi_xcvr_refclk_mux_rbc.tcl/ct3_hssi_xcvr_refclk_mux_simple.tcl/ct3_hssi_xcvr_simple.tcl/gdr_hssi_common_util.tcl/gdr_hssi_parameters.tcl/rnr_hssi_common_util.tcl/rnr_hssi_parameters.tcl/whr_hssi_aibnd_rx_rbc.tcl/whr_hssi_aibnd_rx_simple.tcl/whr_hssi_aibnd_tx_rbc.tcl/whr_hssi_aibnd_tx_simple.tcl/whr_hssi_avmm1_if_rbc.tcl/whr_hssi_avmm1_if_simple.tcl/whr_hssi_avmm2_if_rbc.tcl/whr_hssi_avmm2_if_simple.tcl/whr_hssi_common_util.tcl/whr_hssi_ctp_rbc.tcl/whr_hssi_ctp_simple.tcl/whr_hssi_param_mapping_util.tcl/whr_hssi_parameters.tcl/whr_hssi_pldadapt_rx_rbc.tcl/whr_hssi_pldadapt_rx_simple.tcl/whr_hssi_pldadapt_tx_rbc.tcl/whr_hssi_pldadapt_tx_simple.tcl

filetypes:
  ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff


filenames: HAL/altera_avalon_sysid_sw.tcl/class.ptf/em_sysid.pl/inc
filetypes: dfffd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/sopc_builder_ip/altera_avalon_sysid


filenames: src_hdl
filetypes: d
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/vip/ip_library/common_hdl/aldec/modules/alt_vip_common_fifo


filenames: intel_pcie_pipestage.sv
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/intel_pcie/soft_switch/sep/rtl/common/pipestage


filetypes: ffffffffffffffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/intel_pcie/ptile/common/rtl/cadence/whr_adapters/adapter_gen4x8

filenames:
  alt_mlab.v/intel_pcie_whr_gen4x8_adapter.sv/intel_pcie_whr_gen4x8_cfg_if.sv/intel_pcie_whr_gen4x8_cii_if.sv/intel_pcie_whr_gen4x8_credit_if.sv/intel_pcie_whr_gen4x8_dcfifo.sv/intel_pcie_whr_gen4x8_error_if.sv/intel_pcie_whr_gen4x8_flr_if.sv/intel_pcie_whr_gen4x8_gpx3.sv/intel_pcie_whr_gen4x8_hard_ip_status_if.sv/intel_pcie_whr_gen4x8_hot_plug_if.sv/intel_pcie_whr_gen4x8_int_if.sv/intel_pcie_whr_gen4x8_pm_if.sv/intel_pcie_whr_gen4x8_prs_if.sv/intel_pcie_whr_gen4x8_rx_st_if.sv/intel_pcie_whr_gen4x8_sync_bit.sv/intel_pcie_whr_gen4x8_sync_pulse.sv/intel_pcie_whr_gen4x8_sync_vec.sv/intel_pcie_whr_gen4x8_tx_st_if.sv/intel_pcie_whr_gen4x8_vferr_if.sv


filenames: vcs
filetypes: d
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/ethernet/alt_em10g32/example_design/LL10G_LINESIDE/simulation/ed_sim/synopsys


filenames: inc/src
filetypes: dd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/sopc_builder_ip/altera_avalon_fifo/HAL


filenames: avmmReady/baseLimitCmp/nstageCmp/pipestage
filetypes: dddd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/intel_pcie/soft_switch/sep/rtl/aldec/common


filenames: csr/efc/mac/pcs/top
filetypes: ddddd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/ethernet/alt_e25s10/25g/synopsys/rtl


filetypes: ffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/vip/ip_library/component_ip/utility/alt_vip_line_buffer/aldec/src_hdl

filenames:
[cell repeats an earlier one in this file: 124 characters]


filetypes: ffffffd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/sopc_builder_ip/verification/altera_avalon_mm_slave_bfm

filenames:
[cell repeats an earlier one in this file: 242 characters]


filenames: src_hdl
filetypes: d
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/vip/ip_library/common_hdl/modules/alt_vip_common_sad_tree


filetypes: ddffdd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/alt_eth_40g_100g/100gbe/rtl_src/phy/pma_siv

filenames:
[cell repeats an earlier one in this file: 115 characters]


filenames: alt_vip_crs_422_drop_pad.sv
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/vip/ip_library/component_ip/processing/alt_vip_crs_422_drop_pad/mentor/src_hdl


filenames: terp
filetypes: d
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/alt_xcvr/altera_xcvr_pll/altera_xcvr_cdr_pll_s20/source


filenames: intel_pcie_adapter_rx_if.sv/intel_pcie_adapter_stos.sv/intel_pcie_adapter_tx_if.sv
filetypes: fff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/intel_pcie/ptile/common/rtl/cadence/whr_adapters/adapter_single_segment


filetypes: ff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/ethernet/altera_eth_tse/example_project/common/hw_design/address_decoder/ip/address_decoder_multi_channel/address_decoder_multi_channel_channel_2

filenames:
  address_decoder_multi_channel_channel_2.v/address_decoder_multi_channel_channel_2_altera_merlin_slave_translator_191_x56fcki.sv


filenames: altera_avalon_st_monitor_vhdl.vhd/altera_avalon_st_monitor_vhdl_pkg.vhd
filetypes: ff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/sopc_builder_ip/verification/altera_avalon_st_monitor_bfm_vhdl


filenames: src_hdl
filetypes: d
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/vip/ip_library/component_ip/processing/alt_vip_mix_alg_core/synopsys


filenames: optics_control.v/two_wire_control.v/two_wire_control_tb.sv/two_wire_iopad.v
filetypes: ffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/ethernet/alt_em10g32/example_design/LL10G_1G_10G_LINESIDE_1588v2/rtl/two_wire_serial_controller


filetypes: ffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/dynamic_reconfiguration/dr_f/mentor/rtl/dr_lib

filenames:
[cell repeats an earlier one in this file: 198 characters]


filetypes: fdffffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/altera_hdmi/src/hdmi_2.0/rx/mentor

filenames:
[cell repeats an earlier one in this file: 310 characters]


filenames: basic.tcl/reset.tcl/status.tcl
filetypes: fff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/ethernet/alt_e2550/example_project/hwtest/50g


filenames: intel_pcie_pipestage.sv
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/intel_pcie/soft_switch/sep/rtl/synopsys/common/pipestage


filetypes: ffffffffdff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/ethernet/alt_em10g32/example_design/LL10G_1G_10G_LINESIDE_1588v2/rtl/eth_traffic_controller/eth_std_traffic_controller/crc32

filenames:
[cell repeats an earlier one in this file: 188 characters]


filenames: altera_eth_tse_pcs_2xtbi.v
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/ethernet/tse_ucores/altera_eth_tse_pcs_2xtbi/aldec


filenames: main.tcl/reg_map_inc.tcl
filetypes: ff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/ethernet/alt_e40/example_project/hwtest/altera/sval_top


filenames: cm_rule_basic_enhanced_pcs.tcl/cm_rule_basic_enhanced_pcs_tb.tcl
filetypes: ff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_s20_common_design_example_rules/cm_rule_basic_enhanced_pcs


filenames: src_hdl
filetypes: d
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/vip/ip_library/component_ip/utility/alt_vip_packet_transfer/cadence


filenames: altera_cic_ii_helper.tcl/altera_cic_ii_parameters.tcl/altera_cic_parameters.tcl
filetypes: fff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/dsp/altera_cic_ii/src/tcl_libs


filenames: intel_vvp_protocol_conv.c
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/vvp/component_library/tcl_cores/intel_vvp_protocol_conv/sw/src


filenames: intel_vvp_axi_slave_stub.sv
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filenames: inc/src
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dirname:
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filenames: src_hdl
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filenames: src_hdl
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filenames: llr_CR=1by3_Z=384_BG1.orig.txt/llr_CR=1by3_Z=384_BG1.txt/msg_CR=1by3_Z=384_BG1.txt
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filenames: altera_up_avalon_video_test_pattern_hw.tcl/hdl
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filenames:
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dirname: /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/quartus/common/devinfo/14nm/nd4h
filenames:
  bcm2bits_db/db_nd4h_b_e_mx_esfbga2912c_parasitic.db/db_nd4h_b_e_mx_v_esfbga2912c_parasitic.db/db_nd4h_b_e_mx_vfbga2912c_parasitic.db/db_nd4h_b_e_mxfbga2912c_parasitic.db/db_nd4h_b_h_mx_esfbga2597a_parasitic.db/db_nd4h_b_h_mx_esfbga2597b_parasitic.db/db_nd4h_b_h_mx_v_esfbga2597a_parasitic.db/db_nd4h_b_h_mx_vfbga2597a_parasitic.db/db_nd4h_b_h_mx_vfbga2597b_parasitic.db/db_nd4h_b_h_mxfbga2597a_parasitic.db/db_nd4h_b_h_mxfbga2597b_parasitic.db/db_nd4h_bpm_15_esfbga2254_parasitic.db/db_nd4h_bpm_20_esfbga2217_parasitic.db/db_nd4h_bpm_esfbga2254_parasitic.db/db_nd4h_bpmfbga2217_parasitic.db/db_nd4h_c_h_mx_esfbga2597c_parasitic.db/db_nd4h_c_h_mx_v_esfbga2597c_parasitic.db/db_nd4h_c_h_mx_vfbga2597c_parasitic.db/db_nd4h_c_h_mxfbga2597c_parasitic.db/db_nd4h_e_gt_esfbga2397c_parasitic.db/db_nd4h_e_gt_vfbga2112b_parasitic.db/db_nd4h_e_gt_vfbga2397c_parasitic.db/db_nd4h_e_gtfbga2112b_parasitic.db/db_nd4h_e_gtfbga2397c_parasitic.db/db_nd4h_h_gx_v_eccnfbga1760_parasitic.db/db_nd4h_h_gx_vfbga1760_parasitic.db/db_nd4h_h_gx_vfbga2397b_parasitic.db/db_nd4h_h_gxfbga1760_parasitic.db/db_nd4h_h_gxfbga2397b_parasitic.db/db_nd4h_k_e_mx_esfbga2912c_parasitic.db/db_nd4h_k_e_mxfbga2912c_parasitic.db/db_nd4h_k_h_mx_esfbga2597a_parasitic.db/db_nd4h_k_h_mx_esfbga2597b_parasitic.db/db_nd4h_k_h_mx_i1fbga2597a_parasitic.db/db_nd4h_k_h_mx_i1fbga2597b_parasitic.db/db_nd4h_k_h_mx_v_esfbga2597a_parasitic.db/db_nd4h_k_h_mx_vfbga2597a_parasitic.db/db_nd4h_k_h_mxfbga2597a_parasitic.db/db_nd4h_k_h_mxfbga2597b_parasitic.db/db_nd4h_l_h_mx_esfbga2597c_parasitic.db/db_nd4h_l_h_mx_v_esfbga2597c_parasitic.db/db_nd4h_l_h_mx_vfbga2597c_parasitic.db/db_nd4h_l_h_mxfbga2597c_parasitic.db/db_nd4h_p_dxfbga2597d_parasitic.db/db_nd4hfbga2397v_parasitic.db/db_nd4hfbga2597a_parasitic.db/db_nd4hfbga2597b_parasitic.db/db_nd4hfbga2597c_parasitic.db/ddb_dspf_re_reduced_graph.ddb/ddb_nd4h-1_reva_900mv_0c.dmf.ddb/ddb_nd4h-1_reva_900mv_0c_fdi.ddb/ddb_nd4h-1_reva_900mv_100c.dmf.ddb/ddb_nd4h-1_reva_900mv_100c_dem.ddb/ddb_nd4h-1_reva_900mv_100c_fdi.ddb/ddb_nd4h-1_reva_900mv_110c.dmf.ddb/ddb_nd4h-1_reva_900mv_125c.dmf.ddb/ddb_nd4h-1_reva_900mv_n40c.dmf.ddb/ddb_nd4h-1_reva_vid1_0c.dmf.ddb/ddb_nd4h-1_reva_vid1_0c_fdi.ddb/ddb_nd4h-1_reva_vid1_100c.dmf.ddb/ddb_nd4h-1_reva_vid1_100c_fdi.ddb/ddb_nd4h-1_reva_vid1_110c.dmf.ddb/ddb_nd4h-1_reva_vid1_125c.dmf.ddb/ddb_nd4h-1_reva_vid1_n40c.dmf.ddb/ddb_nd4h-1_revb_900mv_0c.dmf.ddb/ddb_nd4h-1_revb_900mv_100c.dmf.ddb/ddb_nd4h-1_revb_900mv_110c.dmf.ddb/ddb_nd4h-1_revb_900mv_125c.dmf.ddb/ddb_nd4h-1_revb_900mv_n40c.dmf.ddb/ddb_nd4h-1_revb_vid1_0c.dmf.ddb/ddb_nd4h-1_revb_vid1_100c.dmf.ddb/ddb_nd4h-1_revb_vid1_110c.dmf.ddb/ddb_nd4h-1_revb_vid1_125c.dmf.ddb/ddb_nd4h-1_revb_vid1_n40c.dmf.ddb/ddb_nd4h-1_reves_900mv_0c.dmf.ddb/ddb_nd4h-1_reves_900mv_100c.dmf.ddb/ddb_nd4h-1_reves_900mv_110c.dmf.ddb/ddb_nd4h-1_reves_900mv_125c.dmf.ddb/ddb_nd4h-1_reves_900mv_n40c.dmf.ddb/ddb_nd4h-1_reves_vid1_0c.dmf.ddb/ddb_nd4h-1_reves_vid1_100c.dmf.ddb/ddb_nd4h-1_reves_vid1_110c.dmf.ddb/ddb_nd4h-1_reves_vid1_125c.dmf.ddb/ddb_nd4h-1_reves_vid1_n40c.dmf.ddb/ddb_nd4h-1_revesa_900mv_0c.dmf.ddb/ddb_nd4h-1_revesa_900mv_0c_fdi.ddb/ddb_nd4h-1_revesa_900mv_100c.dmf.ddb/ddb_nd4h-1_revesa_900mv_100c_dem.ddb/ddb_nd4h-1_revesa_900mv_100c_fdi.ddb/ddb_nd4h-1_revesa_900mv_110c.dmf.ddb/ddb_nd4h-1_revesa_900mv_125c.dmf.ddb/ddb_nd4h-1_revesa_900mv_n40c.dmf.ddb/ddb_nd4h-1_revesa_vid1_0c.dmf.ddb/ddb_nd4h-1_revesa_vid1_0c_fdi.ddb/ddb_nd4h-1_revesa_vid1_100c.dmf.ddb/ddb_nd4h-1_revesa_vid1_100c_fdi.ddb/ddb_nd4h-1_revesa_vid1_110c.dmf.ddb/ddb_nd4h-1_revesa_vid1_125c.dmf.ddb/ddb_nd4h-1_revesa_vid1_n40c.dmf.ddb/ddb_nd4h-1_revprod_900mv_0c.dmf.ddb/ddb_nd4h-1_revprod_900mv_0c_fdi.ddb/ddb_nd4h-1_revprod_900mv_100c.dmf.ddb/ddb_nd4h-1_revprod_900mv_100c_dem.ddb/ddb_nd4h-1_revprod_900mv_100c_fdi.ddb/ddb_nd4h-1_revprod_900mv_110c.dmf.ddb/ddb_nd4h-1_revprod_900mv_110c_dem.ddb/ddb_nd4h-1_revprod_900mv_110c_fdi.ddb/ddb_nd4h-1_revprod_900mv_125c.dmf.ddb/ddb_nd4h-1_revprod_900mv_n40c.dmf.ddb/ddb_nd4h-1_revprod_900mv_n40c_fdi.ddb/ddb_nd4h-1_revprod_vid1_0c.dmf.ddb/ddb_nd4h-1_revprod_vid1_0c_fdi.ddb/ddb_nd4h-1_revprod_vid1_100c.dmf.ddb/ddb_nd4h-1_revprod_vid1_100c_fdi.ddb/ddb_nd4h-1_revprod_vid1_110c.dmf.ddb/ddb_nd4h-1_revprod_vid1_110c_fdi.ddb/ddb_nd4h-1_revprod_vid1_125c.dmf.ddb/ddb_nd4h-1_revprod_vid1_n40c.dmf.ddb/ddb_nd4h-1_revprod_vid1_n40c_fdi.ddb/ddb_nd4h-2_reva_850mv_0c.dmf.ddb/ddb_nd4h-2_reva_850mv_100c.dmf.ddb/ddb_nd4h-2_reva_850mv_110c.dmf.ddb/ddb_nd4h-2_reva_850mv_125c.dmf.ddb/ddb_nd4h-2_reva_850mv_n40c.dmf.ddb/ddb_nd4h-2_reva_900mv_0c.dmf.ddb/ddb_nd4h-2_reva_900mv_0c_fdi.ddb/ddb_nd4h-2_reva_900mv_100c.dmf.ddb/ddb_nd4h-2_reva_900mv_100c_dem.ddb/ddb_nd4h-2_reva_900mv_100c_fdi.ddb/ddb_nd4h-2_reva_900mv_110c.dmf.ddb/ddb_nd4h-2_reva_900mv_125c.dmf.ddb/ddb_nd4h-2_reva_900mv_n40c.dmf.ddb/ddb_nd4h-2_reva_900mv_n40c_fdi.ddb/ddb_nd4h-2_reva_vid2_0c.dmf.ddb/ddb_nd4h-2_reva_vid2_100c.dmf.ddb/ddb_nd4h-2_reva_vid2_110c.dmf.ddb/ddb_nd4h-2_reva_vid2_125c.dmf.ddb/ddb_nd4h-2_reva_vid2_n40c.dmf.ddb/ddb_nd4h-2_revb_850mv_0c.dmf.ddb/ddb_nd4h-2_revb_850mv_100c.dmf.ddb/ddb_nd4h-2_revb_850mv_110c.dmf.ddb/ddb_nd4h-2_revb_850mv_125c.dmf.ddb/ddb_nd4h-2_revb_850mv_n40c.dmf.ddb/ddb_nd4h-2_revb_900mv_0c.dmf.ddb/ddb_nd4h-2_revb_900mv_100c.dmf.ddb/ddb_nd4h-2_revb_900mv_110c.dmf.ddb/ddb_nd4h-2_revb_900mv_125c.dmf.ddb/ddb_nd4h-2_revb_900mv_n40c.dmf.ddb/ddb_nd4h-2_revb_vid2_0c.dmf.ddb/ddb_nd4h-2_revb_vid2_100c.dmf.ddb/ddb_nd4h-2_revb_vid2_110c.dmf.ddb/ddb_nd4h-2_revb_vid2_125c.dmf.ddb/ddb_nd4h-2_revb_vid2_n40c.dmf.ddb/ddb_nd4h-2_reves_850mv_0c.dmf.ddb/ddb_nd4h-2_reves_850mv_100c.dmf.ddb/ddb_nd4h-2_reves_850mv_110c.dmf.ddb/ddb_nd4h-2_reves_850mv_125c.dmf.ddb/ddb_nd4h-2_reves_850mv_n40c.dmf.ddb/ddb_nd4h-2_reves_900mv_0c.dmf.ddb/ddb_nd4h-2_reves_900mv_100c.dmf.ddb/ddb_nd4h-2_reves_900mv_110c.dmf.ddb/ddb_nd4h-2_reves_900mv_125c.dmf.ddb/ddb_nd4h-2_reves_900mv_n40c.dmf.ddb/ddb_nd4h-2_reves_vid2_0c.dmf.ddb/ddb_nd4h-2_reves_vid2_100c.dmf.ddb/ddb_nd4h-2_reves_vid2_110c.dmf.ddb/ddb_nd4h-2_reves_vid2_125c.dmf.ddb/ddb_nd4h-2_reves_vid2_n40c.dmf.ddb/ddb_nd4h-2_revesa_850mv_0c.dmf.ddb/ddb_nd4h-2_revesa_850mv_0c_fdi.ddb/ddb_nd4h-2_revesa_850mv_100c.dmf.ddb/ddb_nd4h-2_revesa_850mv_100c_dem.ddb/ddb_nd4h-2_revesa_850mv_100c_fdi.ddb/ddb_nd4h-2_revesa_850mv_110c.dmf.ddb/ddb_nd4h-2_revesa_850mv_110c_dem.ddb/ddb_nd4h-2_revesa_850mv_110c_fdi.ddb/ddb_nd4h-2_revesa_850mv_125c.dmf.ddb/ddb_nd4h-2_revesa_850mv_n40c.dmf.ddb/ddb_nd4h-2_revesa_900mv_0c.dmf.ddb/ddb_nd4h-2_revesa_900mv_0c_fdi.ddb/ddb_nd4h-2_revesa_900mv_100c.dmf.ddb/ddb_nd4h-2_revesa_900mv_100c_dem.ddb/ddb_nd4h-2_revesa_900mv_100c_fdi.ddb/ddb_nd4h-2_revesa_900mv_110c.dmf.ddb/ddb_nd4h-2_revesa_900mv_110c_dem.ddb/ddb_nd4h-2_revesa_900mv_110c_fdi.ddb/ddb_nd4h-2_revesa_900mv_125c.dmf.ddb/ddb_nd4h-2_revesa_900mv_n40c.dmf.ddb/ddb_nd4h-2_revesa_vid2_0c.dmf.ddb/ddb_nd4h-2_revesa_vid2_0c_fdi.ddb/ddb_nd4h-2_revesa_vid2_100c.dmf.ddb/ddb_nd4h-2_revesa_vid2_100c_fdi.ddb/ddb_nd4h-2_revesa_vid2_110c.dmf.ddb/ddb_nd4h-2_revesa_vid2_110c_fdi.ddb/ddb_nd4h-2_revesa_vid2_125c.dmf.ddb/ddb_nd4h-2_revesa_vid2_n40c.dmf.ddb/ddb_nd4h-2_revprod_850mv_0c.dmf.ddb/ddb_nd4h-2_revprod_850mv_0c_fdi.ddb/ddb_nd4h-2_revprod_850mv_100c.dmf.ddb/ddb_nd4h-2_revprod_850mv_100c_dem.ddb/ddb_nd4h-2_revprod_850mv_100c_fdi.ddb/ddb_nd4h-2_revprod_850mv_110c.dmf.ddb/ddb_nd4h-2_revprod_850mv_110c_dem.ddb/ddb_nd4h-2_revprod_850mv_110c_fdi.ddb/ddb_nd4h-2_revprod_850mv_125c.dmf.ddb/ddb_nd4h-2_revprod_850mv_n40c.dmf.ddb/ddb_nd4h-2_revprod_850mv_n40c_fdi.ddb/ddb_nd4h-2_revprod_900mv_0c.dmf.ddb/ddb_nd4h-2_revprod_900mv_0c_fdi.ddb/ddb_nd4h-2_revprod_900mv_100c.dmf.ddb/ddb_nd4h-2_revprod_900mv_100c_dem.ddb/ddb_nd4h-2_revprod_900mv_100c_fdi.ddb/ddb_nd4h-2_revprod_900mv_110c.dmf.ddb/ddb_nd4h-2_revprod_900mv_110c_dem.ddb/ddb_nd4h-2_revprod_900mv_110c_fdi.ddb/ddb_nd4h-2_revprod_900mv_125c.dmf.ddb/ddb_nd4h-2_revprod_900mv_n40c.dmf.ddb/ddb_nd4h-2_revprod_900mv_n40c_fdi.ddb/ddb_nd4h-2_revprod_vid2_0c.dmf.ddb/ddb_nd4h-2_revprod_vid2_0c_fdi.ddb/ddb_nd4h-2_revprod_vid2_100c.dmf.ddb/ddb_nd4h-2_revprod_vid2_100c_fdi.ddb/ddb_nd4h-2_revprod_vid2_110c.dmf.ddb/ddb_nd4h-2_revprod_vid2_110c_fdi.ddb/ddb_nd4h-2_revprod_vid2_125c.dmf.ddb/ddb_nd4h-2_revprod_vid2_n40c.dmf.ddb/ddb_nd4h-2_revprod_vid2_n40c_fdi.ddb/ddb_nd4h-3_reva_850mv_0c.dmf.ddb/ddb_nd4h-3_reva_850mv_100c.dmf.ddb/ddb_nd4h-3_reva_850mv_110c.dmf.ddb/ddb_nd4h-3_reva_850mv_125c.dmf.ddb/ddb_nd4h-3_reva_850mv_n40c.dmf.ddb/ddb_nd4h-3_reva_900mv_0c.dmf.ddb/ddb_nd4h-3_reva_900mv_100c.dmf.ddb/ddb_nd4h-3_reva_900mv_110c.dmf.ddb/ddb_nd4h-3_reva_900mv_125c.dmf.ddb/ddb_nd4h-3_reva_900mv_n40c.dmf.ddb/ddb_nd4h-3_reva_vid3a_0c.dmf.ddb/ddb_nd4h-3_reva_vid3a_100c.dmf.ddb/ddb_nd4h-3_reva_vid3a_110c.dmf.ddb/ddb_nd4h-3_reva_vid3a_125c.dmf.ddb/ddb_nd4h-3_reva_vid3a_n40c.dmf.ddb/ddb_nd4h-3_revb_850mv_0c.dmf.ddb/ddb_nd4h-3_revb_850mv_100c.dmf.ddb/ddb_nd4h-3_revb_850mv_110c.dmf.ddb/ddb_nd4h-3_revb_850mv_125c.dmf.ddb/ddb_nd4h-3_revb_850mv_n40c.dmf.ddb/ddb_nd4h-3_revb_900mv_0c.dmf.ddb/ddb_nd4h-3_revb_900mv_100c.dmf.ddb/ddb_nd4h-3_revb_900mv_110c.dmf.ddb/ddb_nd4h-3_revb_900mv_125c.dmf.ddb/ddb_nd4h-3_revb_900mv_n40c.dmf.ddb/ddb_nd4h-3_revb_vid3a_0c.dmf.ddb/ddb_nd4h-3_revb_vid3a_100c.dmf.ddb/ddb_nd4h-3_revb_vid3a_110c.dmf.ddb/ddb_nd4h-3_revb_vid3a_125c.dmf.ddb/ddb_nd4h-3_revb_vid3a_n40c.dmf.ddb/ddb_nd4h-3_reves_850mv_0c.dmf.ddb/ddb_nd4h-3_reves_850mv_100c.dmf.ddb/ddb_nd4h-3_reves_850mv_110c.dmf.ddb/ddb_nd4h-3_reves_850mv_125c.dmf.ddb/ddb_nd4h-3_reves_850mv_n40c.dmf.ddb/ddb_nd4h-3_reves_900mv_0c.dmf.ddb/ddb_nd4h-3_reves_900mv_100c.dmf.ddb/ddb_nd4h-3_reves_900mv_110c.dmf.ddb/ddb_nd4h-3_reves_900mv_125c.dmf.ddb/ddb_nd4h-3_reves_900mv_n40c.dmf.ddb/ddb_nd4h-3_reves_vid3a_0c.dmf.ddb/ddb_nd4h-3_reves_vid3a_100c.dmf.ddb/ddb_nd4h-3_reves_vid3a_110c.dmf.ddb/ddb_nd4h-3_reves_vid3a_125c.dmf.ddb/ddb_nd4h-3_reves_vid3a_n40c.dmf.ddb/ddb_nd4h-3_revesa_850mv_0c.dmf.ddb/ddb_nd4h-3_revesa_850mv_100c.dmf.ddb/ddb_nd4h-3_revesa_850mv_110c.dmf.ddb/ddb_nd4h-3_revesa_850mv_125c.dmf.ddb/ddb_nd4h-3_revesa_850mv_n40c.dmf.ddb/ddb_nd4h-3_revesa_900mv_0c.dmf.ddb/ddb_nd4h-3_revesa_900mv_0c_fdi.ddb/ddb_nd4h-3_revesa_900mv_100c.dmf.ddb/ddb_nd4h-3_revesa_900mv_100c_dem.ddb/ddb_nd4h-3_revesa_900mv_100c_fdi.ddb/ddb_nd4h-3_revesa_900mv_110c.dmf.ddb/ddb_nd4h-3_revesa_900mv_125c.dmf.ddb/ddb_nd4h-3_revesa_900mv_n40c.dmf.ddb/ddb_nd4h-3_revesa_vid3a_0c.dmf.ddb/ddb_nd4h-3_revesa_vid3a_0c_fdi.ddb/ddb_nd4h-3_revesa_vid3a_100c.dmf.ddb/ddb_nd4h-3_revesa_vid3a_100c_fdi.ddb/ddb_nd4h-3_revesa_vid3a_110c.dmf.ddb/ddb_nd4h-3_revesa_vid3a_125c.dmf.ddb/ddb_nd4h-3_revesa_vid3a_n40c.dmf.ddb/ddb_nd4h-3_revprod_850mv_0c.dmf.ddb/ddb_nd4h-3_revprod_850mv_0c_fdi.ddb/ddb_nd4h-3_revprod_850mv_100c.dmf.ddb/ddb_nd4h-3_revprod_850mv_100c_dem.ddb/ddb_nd4h-3_revprod_850mv_100c_fdi.ddb/ddb_nd4h-3_revprod_850mv_110c.dmf.ddb/ddb_nd4h-3_revprod_850mv_110c_dem.ddb/ddb_nd4h-3_revprod_850mv_110c_fdi.ddb/ddb_nd4h-3_revprod_850mv_125c.dmf.ddb/ddb_nd4h-3_revprod_850mv_n40c.dmf.ddb/ddb_nd4h-3_revprod_850mv_n40c_fdi.ddb/ddb_nd4h-3_revprod_900mv_0c.dmf.ddb/ddb_nd4h-3_revprod_900mv_0c_fdi.ddb/ddb_nd4h-3_revprod_900mv_100c.dmf.ddb/ddb_nd4h-3_revprod_900mv_100c_dem.ddb/ddb_nd4h-3_revprod_900mv_100c_fdi.ddb/ddb_nd4h-3_revprod_900mv_110c.dmf.ddb/ddb_nd4h-3_revprod_900mv_110c_dem.ddb/ddb_nd4h-3_revprod_900mv_110c_fdi.ddb/ddb_nd4h-3_revprod_900mv_125c.dmf.ddb/ddb_nd4h-3_revprod_900mv_n40c.dmf.ddb/ddb_nd4h-3_revprod_900mv_n40c_fdi.ddb/ddb_nd4h-3_revprod_vid3a_0c.dmf.ddb/ddb_nd4h-3_revprod_vid3a_0c_fdi.ddb/ddb_nd4h-3_revprod_vid3a_100c.dmf.ddb/ddb_nd4h-3_revprod_vid3a_100c_fdi.ddb/ddb_nd4h-3_revprod_vid3a_110c.dmf.ddb/ddb_nd4h-3_revprod_vid3a_110c_fdi.ddb/ddb_nd4h-3_revprod_vid3a_125c.dmf.ddb/ddb_nd4h-3_revprod_vid3a_n40c.dmf.ddb/ddb_nd4h-3_revprod_vid3a_n40c_fdi.ddb/ddb_nd4h-ff_reva_800mv_0c.dmf.ddb/ddb_nd4h-ff_reva_800mv_100c.dmf.ddb/ddb_nd4h-ff_reva_800mv_110c.dmf.ddb/ddb_nd4h-ff_reva_800mv_125c.dmf.ddb/ddb_nd4h-ff_reva_800mv_n40c.dmf.ddb/ddb_nd4h-ff_reva_850mv_0c.dmf.ddb/ddb_nd4h-ff_reva_850mv_100c.dmf.ddb/ddb_nd4h-ff_reva_850mv_110c.dmf.ddb/ddb_nd4h-ff_reva_850mv_125c.dmf.ddb/ddb_nd4h-ff_reva_850mv_n40c.dmf.ddb/ddb_nd4h-ff_reva_900mv_0c.dmf.ddb/ddb_nd4h-ff_reva_900mv_100c.dmf.ddb/ddb_nd4h-ff_reva_900mv_110c.dmf.ddb/ddb_nd4h-ff_reva_900mv_125c.dmf.ddb/ddb_nd4h-ff_reva_900mv_n40c.dmf.ddb/ddb_nd4h-ff_reva_vid1_0c.dmf.ddb/ddb_nd4h-ff_reva_vid1_100c.dmf.ddb/ddb_nd4h-ff_reva_vid1_110c.dmf.ddb/ddb_nd4h-ff_reva_vid1_125c.dmf.ddb/ddb_nd4h-ff_reva_vid1_n40c.dmf.ddb/ddb_nd4h-ff_revb_800mv_0c.dmf.ddb/ddb_nd4h-ff_revb_800mv_100c.dmf.ddb/ddb_nd4h-ff_revb_800mv_110c.dmf.ddb/ddb_nd4h-ff_revb_800mv_125c.dmf.ddb/ddb_nd4h-ff_revb_800mv_n40c.dmf.ddb/ddb_nd4h-ff_revb_850mv_0c.dmf.ddb/ddb_nd4h-ff_revb_850mv_100c.dmf.ddb/ddb_nd4h-ff_revb_850mv_110c.dmf.ddb/ddb_nd4h-ff_revb_850mv_125c.dmf.ddb/ddb_nd4h-ff_revb_850mv_n40c.dmf.ddb/ddb_nd4h-ff_revb_900mv_0c.dmf.ddb/ddb_nd4h-ff_revb_900mv_100c.dmf.ddb/ddb_nd4h-ff_revb_900mv_110c.dmf.ddb/ddb_nd4h-ff_revb_900mv_125c.dmf.ddb/ddb_nd4h-ff_revb_900mv_n40c.dmf.ddb/ddb_nd4h-ff_revb_vid1_0c.dmf.ddb/ddb_nd4h-ff_revb_vid1_100c.dmf.ddb/ddb_nd4h-ff_revb_vid1_110c.dmf.ddb/ddb_nd4h-ff_revb_vid1_125c.dmf.ddb/ddb_nd4h-ff_revb_vid1_n40c.dmf.ddb/ddb_nd4h-ff_reves_800mv_0c.dmf.ddb/ddb_nd4h-ff_reves_800mv_100c.dmf.ddb/ddb_nd4h-ff_reves_800mv_110c.dmf.ddb/ddb_nd4h-ff_reves_800mv_125c.dmf.ddb/ddb_nd4h-ff_reves_800mv_n40c.dmf.ddb/ddb_nd4h-ff_reves_850mv_0c.dmf.ddb/ddb_nd4h-ff_reves_850mv_100c.dmf.ddb/ddb_nd4h-ff_reves_850mv_110c.dmf.ddb/ddb_nd4h-ff_reves_850mv_125c.dmf.ddb/ddb_nd4h-ff_reves_850mv_n40c.dmf.ddb/ddb_nd4h-ff_reves_900mv_0c.dmf.ddb/ddb_nd4h-ff_reves_900mv_100c.dmf.ddb/ddb_nd4h-ff_reves_900mv_110c.dmf.ddb/ddb_nd4h-ff_reves_900mv_125c.dmf.ddb/ddb_nd4h-ff_reves_900mv_n40c.dmf.ddb/ddb_nd4h-ff_reves_vid1_0c.dmf.ddb/ddb_nd4h-ff_reves_vid1_100c.dmf.ddb/ddb_nd4h-ff_reves_vid1_110c.dmf.ddb/ddb_nd4h-ff_reves_vid1_125c.dmf.ddb/ddb_nd4h-ff_reves_vid1_n40c.dmf.ddb/ddb_nd4h-ff_revesa_800mv_0c.dmf.ddb/ddb_nd4h-ff_revesa_800mv_100c.dmf.ddb/ddb_nd4h-ff_revesa_800mv_110c.dmf.ddb/ddb_nd4h-ff_revesa_800mv_125c.dmf.ddb/ddb_nd4h-ff_revesa_800mv_n40c.dmf.ddb/ddb_nd4h-ff_revesa_850mv_0c.dmf.ddb/ddb_nd4h-ff_revesa_850mv_100c.dmf.ddb/ddb_nd4h-ff_revesa_850mv_110c.dmf.ddb/ddb_nd4h-ff_revesa_850mv_125c.dmf.ddb/ddb_nd4h-ff_revesa_850mv_n40c.dmf.ddb/ddb_nd4h-ff_revesa_900mv_0c.dmf.ddb/ddb_nd4h-ff_revesa_900mv_100c.dmf.ddb/ddb_nd4h-ff_revesa_900mv_110c.dmf.ddb/ddb_nd4h-ff_revesa_900mv_125c.dmf.ddb/ddb_nd4h-ff_revesa_900mv_n40c.dmf.ddb/ddb_nd4h-ff_revesa_vid1_0c.dmf.ddb/ddb_nd4h-ff_revesa_vid1_100c.dmf.ddb/ddb_nd4h-ff_revesa_vid1_110c.dmf.ddb/ddb_nd4h-ff_revesa_vid1_125c.dmf.ddb/ddb_nd4h-ff_revesa_vid1_n40c.dmf.ddb/ddb_nd4h-ff_revprod_800mv_0c.dmf.ddb/ddb_nd4h-ff_revprod_800mv_100c.dmf.ddb/ddb_nd4h-ff_revprod_800mv_110c.dmf.ddb/ddb_nd4h-ff_revprod_800mv_125c.dmf.ddb/ddb_nd4h-ff_revprod_800mv_n40c.dmf.ddb/ddb_nd4h-ff_revprod_850mv_0c.dmf.ddb/ddb_nd4h-ff_revprod_850mv_100c.dmf.ddb/ddb_nd4h-ff_revprod_850mv_110c.dmf.ddb/ddb_nd4h-ff_revprod_850mv_125c.dmf.ddb/ddb_nd4h-ff_revprod_850mv_n40c.dmf.ddb/ddb_nd4h-ff_revprod_900mv_0c.dmf.ddb/ddb_nd4h-ff_revprod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filetypes:
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filenames: altera_eth_gmii_ptp_inserter.v
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/ethernet/ethernet_ucore/altera_eth_gmii_ptp_inserter/cadence


filetypes: ffffffffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/QuartusPrimePro/21.2/ip/altera/altera_hmcc_mtaps/2f8l/mentor

filenames:
[cell repeats an earlier one in this file: 429 characters]


filenames: alt_e40_jtag_avmm.v/alt_e40_reset_controller.v
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filetypes: ffffffffffffffff
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filenames: cadence/ilk_rx_stripe_adapter.sv/ilk_tx_stripe_adapter.sv/mentor/synopsys
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filenames:
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filenames: llr_CR=1by3_Z=384_BG1.orig.txt/llr_CR=1by3_Z=384_BG1.txt/msg_CR=1by3_Z=384_BG1.txt
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filenames: intel_vvp_core.c
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filenames: rtl
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