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filenames: src_hdl
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filenames: altera_eth_frame_status_merger.v
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filetypes: ffffffffffffffffff
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filenames:
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filenames: README/ex1_back_to_back_sv/ex1_back_to_back_vhd
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filetypes: ffffff
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filenames:
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filenames: src_hdl
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filenames: eth_std_tc/eth_traffic_controller_64.sv/eth_traffic_controller_top.sv
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filenames: alt_e40_phy_pcs.v/common/rx/tx
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filenames: src_hdl
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filetypes: ffffffffff
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filenames:
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filetypes: dddffddffddd
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filenames: testbench_gen_host.vhd/testbench_gen_host_32.vhd
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filenames: address_decoder_multi_channel_channel_6.v/altera_merlin_slave_translator_mch6.sv
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filenames: alt_vip_video_over_film.sv
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dirname:
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filenames: rtl
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filetypes: fffffffffffff
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filenames:
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filenames: altpcie_s10_tbed_bfm_hwtcl.v/altpcie_s10_tbed_hwtcl.v/verilog
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filenames: altera_eth_packet_formatter.v
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dirname:
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filenames: alt_e100_mac_addr_regs.v/alt_e100_mac_csr.v/alt_e100_status_cntr_pause_sync.v
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filenames: hdmi_tx_reg_wrap.v/hdmi_tx_registers
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filenames: avst_credit_endianness_adp.sv.terp/avst_credit_endianness_adp_hw.tcl
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filetypes: ffffffffffffff
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filenames:
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filenames: altera_avalon_spi_regs.h
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filenames: src
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dirname:
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filenames: alt_vip_crs_scheduler.sv
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filenames: altera_up_avalon_character_lcd.c
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filetypes: ffffff
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filenames:
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filenames: common/hwtest/hwtest_sl/templates/testbench
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dirname:
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filenames: alt_vip_common_mult_add.sv
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dirname:
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filenames: src_hdl
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filetypes: fffffffffffffffff
dirname:
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filenames:
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filenames: intel_pcie_lite_bas.sv/intel_pcie_mcdma_bas.sv/intel_pcie_mcdma_bas_wrapper.v
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dirname:
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filenames: automap.ptf/class.ptf/netlist
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dirname:
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filenames: src_hdl
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filenames: src_hdl
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filenames: ast/csr/efc/mac/pcs/top
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filetypes: ddffddddddd
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filenames:
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filenames: ex1_back_to_back_sv/ex1_back_to_back_vhd
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dirname:
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filenames: src_hdl
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filetypes: fffffffff
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filenames:
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filetypes: ffffddfff
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filenames:
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filenames: src_hdl
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filetypes: fffffffffffffffffffffffffff
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filenames:
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filetypes: fffffffffffff
dirname:
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filenames:
  dp2p0_txll_dc_2p_ram.v/dp2p0_txll_dc_2p_ram_cebe.v/dp2p0_txll_dc_2p_ram_mw.v/dp2p0_txll_dc_2p_ram_mw_cebe.v/dp2p0_txll_dcfifo.v/dp2p0_txll_dcfifo_mw.v/dp2p0_txll_sc_1p_ram.v/dp2p0_txll_sc_1p_ram_cebe.v/dp2p0_txll_sc_2p_ram.v/dp2p0_txll_sc_2p_ram_cebe.v/dp2p0_txll_sc_true_2p_ram.v/dp2p0_txll_sc_true_2p_ram_cebe.v/dp2p0_txll_scfifo.v


filenames: rule_basic_standard_pcs.tcl
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filenames: alt_ehipc3_fm_rx_deskew.sv/alt_ehipc3_fm_tx_deskew.sv/alt_ehipc3_fm_word_delay_mlab.sv
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filenames: intel_vvp_guard_bands_scheduler.sv
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filenames: crc24b_wdth.v/fifo_crc_cfg.v/ldpc5g_crc_dec.sv/ldpc5g_crc_dec_top.sv
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filenames: ast/csr/efc/mac/pcs/top
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filenames: alt_aeu_clks_40.v/alt_aeu_fifo_depth_40.v/alt_aeu_ptp_rx_40.v
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filenames: inc/src
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filenames:
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filenames: par/sim/src
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filenames: common/modules
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filenames: altera_eth_fifo.v
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filenames: vcs/vcsmx
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filenames:
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filenames: alt_eth_tse_mac_pcs2xtbi_pma.v/alt_mge_channel.v/alt_mge_multi_channel.sv
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filenames: intel_pcie_cmp_stg123.sv
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filenames: src_hdl
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filenames: altera_eth_tse_mac.v
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filetypes: ffffff
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filetypes: ffffffffffffffffffffff
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filetypes: ffffffffffff
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filetypes: fffffdd
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filenames:
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filetypes: dffddddd
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filenames:
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filenames: alt_mlab.v
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filetypes: dffffdfffff
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filenames:
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filetypes: fffffffffffffffffffff
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filenames:
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filetypes: ffffffff
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filenames:
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filenames: common/mr42/old_arch/r22sdf
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filenames: intel_vvp_slave_data_split.sv
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filetypes: fffffffffffffffffffffffffff
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filenames:
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filenames: intel_fpga_avalon_mm_monitor_tap.sv/intel_fpga_avalon_mm_monitor_tap_hw.tcl
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filetypes: ddfffff
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filenames:
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filenames: parameter.tcl
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filenames: Makefile.txt/ifc_mcdma_testpmd.c/ifc_mcdma_testpmd.h/testpmd.c/testpmd.h
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filenames: includes.h/os_cpu.h
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dirname:
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filenames: common_src/reconfig
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filenames: src_hdl
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filetypes: ffffffffffffffffffffffffffffffffffffffffffff
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filenames: cadence/ilk_12l_10g_rx_stripe_adapter.v/ilk_12l_10g_tx_stripe_adapter.v/intelfpga/mentor/synopsys
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filenames: altera_merlin_waitrequest_adapter.v/altera_merlin_waitrequest_adapter_hw.tcl
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filenames: altera_eth_tse_nd_phyip_terminator.v
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filenames: src_hdl
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filenames: altera_wufi_ufi_adapter.sv
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filenames: soft_lckppm_det.v
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filenames: src_hdl
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dirname:
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filenames:
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filetypes:
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filenames: quartus/rtl
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filenames: alt_vip_video_input_bridge_resp.sv
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filenames: altera_jesd204_pipeline.v
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filenames: altera_eth_mdio.v
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filenames: rtl
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filenames: alt_e40_sys_pll_sv/alt_e40_sys_pll_sv.qip/alt_e40_sys_pll_sv.v
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filetypes: fffffff
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filenames: src_hdl
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filenames: intel_jesd204c_phy_adapter_c3.v/intel_jesd204c_signal_adapter.v
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filenames: cic_ii_fir_comp_coeff.m.terp
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filenames: src_hdl
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dirname:
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filenames: intel_vab_common_pkg.sv
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dirname:
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filenames: src_hdl
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filetypes: dffffffffffffdddd
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filenames:
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filenames:
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filenames: bridge_qsys_script.tcl
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filenames: ddr4.tcl/lpddr4.tcl
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filenames: src_hdl
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filenames: alt_vip_tpg_alg_core.sv
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filenames: dc_fifo_0.ip
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filenames: src_hdl
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filenames: alt_e40_fc_top.v/alt_e40_rx_fc.v/alt_e40_tx_fc.v/alt_e40_tx_fc_frame_muxer.v
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filenames:
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filenames: csr
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filenames: altera_eth_tse_pcs_pma_phyip.v
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filenames: common/modules
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dirname:
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filenames: altera_avalon_pio_regs.h
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dirname:
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filetypes: fffff
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filenames:
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filetypes: fffffff
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filenames:
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filetypes: fffffffffffffffffffff
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filenames:
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filenames: bch_enc_package.vhd/bch_encoder.vhd/bch_encoder_core.vhd
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dirname:
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filetypes: dddddddddf
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filenames:
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filenames: mem_ss_base_csr_regs.sv/mem_ss_csr_top.sv
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filenames: alt_aeu_40_status_sync.v/alt_aeu_40_sync_arst.v
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filenames: auk_dspip_r22sdf_lib_pkg.vhd
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filenames: aldec/alt_vip_cvo_scheduler_hw.tcl/cadence/intelfpga/mentor/src_hdl/synopsys
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filenames: eth_100g_nrz/eth_25g_nrz
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filenames: altera_voltage_sensor_control.sv/voltage_sensor_avalon_control.sv/voltage_sensor_wrapper.sv
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filenames: source
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filenames: avalon_st_loopback_inc.tcl/avalon_st_loopback_reg_map.tcl
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filenames:
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filenames: alt_xcvr_ilk_tx_fifo_util.sv/alt_xcvr_ilk_tx_fifo_util_hw.tcl/alt_xcvr_ilk_tx_fifo_util_top.v
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filenames: spi_hw.tcl
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filetypes: fffffffffffffffff
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filenames:
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filenames: altera_eth_tse_mac.v
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filenames: common/intel_pcie_sep_block_top.sv/sw_config_path/sw_ctrl_path/sw_data_path
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filenames: tb_run.sh/xcelium_wave.tcl
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filenames:
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filenames: alt_vip_packet_demux.sv
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filenames:
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filenames:
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filetypes: ffffffffffffffffffffffffff
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filenames: common/hwtest/templates
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filenames: inc/src
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filenames:
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filetypes: fffffffffffffffffff
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filenames: assignments.tcl.terp
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filetypes: fffffffffffffffffff
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filenames: csrgen_output
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filetypes: fffffffffffffffffffffffffffffffffff
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filenames: intel_vvp_clocked_video_sink_bfm/intel_vvp_clocked_video_source_bfm
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filenames: mon_inc.tcl/mon_reg_map.tcl
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filenames:
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filenames: intel_hdmi_ce.v/intel_hdmi_tx_core_phy_intf.v/intel_hdmi_tx_oversample.v
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filenames: altera_eth_default_slave.v
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filenames: debug_stp/example_design_uflex_s10_board_level
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filenames: cfp_control_inc.tcl/main.tcl
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filenames: alt_aeu_100_ack_skid.v/alt_e100_status_sync.v/alt_e100_sync_arst.v/e100_sync_arst.v/reverse_words.v
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filenames: alt_e50s10_adapt_pma.v/alt_e50s10_eli_jtag.v/alt_e50s10_pll_recal.v/alt_e50s10_reset_controller.v
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filenames: csr/efc/mac/pcs/top
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filenames: optics_control.v/two_wire_control.v/two_wire_control_tb.sv/two_wire_iopad.v
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filenames: ilk_rx_stripe_adapter.sv/ilk_tx_stripe_adapter.sv
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filenames: address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki.sv
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filenames: altera_xcvr_cdr_pll_a10.sv
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filenames: tcl
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filenames: alt_reset_delay.v/device_init.v/edge_detector.sv/output_buf_i2c.tcl.terp/reset_release.tcl.terp
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filenames: altera_avalon_reset_source.sv/altera_avalon_reset_source.vhd/altera_avalon_reset_source_hw.tcl
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filenames: Licenses/Makefile.txt/common/driver/version.txt
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filenames: alt_ehipc2_alias_csr.sv/alt_ehipc2_avmm_32to8.sv/alt_ehipc2_csr.v
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filenames: intel_vvp_tmo_ram_altsyncram.sv/intel_vvp_tmo_ram_avlmm_if.sv
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filenames: src_hdl
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filenames: intel_vvp_clipper_scheduler.sv
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filenames: altera_jesd204_signal_adapter.v
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filenames: alt_vip_cl_packet_dangler.sv
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filetypes: ffffffffffffff
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filenames:
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filenames: alt_e40_block_distributor.v/alt_e40_pcs.v/alt_e40_pcs_rx.v/alt_e40_pcs_tx.v
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filenames: inc/src
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filenames:
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filenames: rtl
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filenames: rtl
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filetypes: ffffff
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filetypes: fdfffffffffffffffffffffffffffffffffffffffff
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filenames:
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filenames: altera_eth_databus_bit_inserter.v/altera_eth_databus_bit_inserter_hw.tcl
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filenames: src_hdl
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filenames: alt_hiconnect_av_mstr_trans.sv/alt_hiconnect_av_mstr_trans_hw.tcl
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filenames: alt_ehipc2_dcfifo_mlab.sv/alt_ehipc2_mlab.sv
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filenames:
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filenames: hmcc_example.qpf/hmcc_example.qsf.terp/hmcc_example.sdc/sysconsole_testbench.tcl
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filenames:
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filenames: alt_vip_common_pip_bunch.sv
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filenames:
  aldec/alt_ntrlkn_12l_6g_align_dcf.v/alt_ntrlkn_12l_6g_align_fifo.v/alt_ntrlkn_12l_6g_alignment_pipe.v/alt_ntrlkn_12l_6g_arbiter.v/alt_ntrlkn_12l_6g_avalon_to_ilk_adapter_4.v/alt_ntrlkn_12l_6g_buffer_1_to_2.v/alt_ntrlkn_12l_6g_buffer_2_to_1.v/alt_ntrlkn_12l_6g_buffered_read_scheduler_4.v/alt_ntrlkn_12l_6g_channel_fifo.v/alt_ntrlkn_12l_6g_compact_words_4.v/alt_ntrlkn_12l_6g_crc24_dat64.v/alt_ntrlkn_12l_6g_crc24_dat64_factor.v/alt_ntrlkn_12l_6g_crc24_dat64_flat.v/alt_ntrlkn_12l_6g_crc24_dat64_only_flat.v/alt_ntrlkn_12l_6g_crc24_multiple_upto2.v/alt_ntrlkn_12l_6g_crc24_multiple_upto3.v/alt_ntrlkn_12l_6g_crc24_multiple_upto4.v/alt_ntrlkn_12l_6g_crc24_multiple_upto5.v/alt_ntrlkn_12l_6g_crc24_zer64_flat.v/alt_ntrlkn_12l_6g_crc24_zer64x10_flat.v/alt_ntrlkn_12l_6g_crc24_zer64x2_flat.v/alt_ntrlkn_12l_6g_crc24_zer64x3_flat.v/alt_ntrlkn_12l_6g_crc24_zer64x4_flat.v/alt_ntrlkn_12l_6g_crc24_zer64x5_flat.v/alt_ntrlkn_12l_6g_crc32c_dat64.v/alt_ntrlkn_12l_6g_crc32c_dat64_factor.v/alt_ntrlkn_12l_6g_crc32c_dat64_flat.v/alt_ntrlkn_12l_6g_crc32c_dat64_only.v/alt_ntrlkn_12l_6g_crc32c_dat64_only_factor.v/alt_ntrlkn_12l_6g_crc32c_dat64_only_flat.v/alt_ntrlkn_12l_6g_crc32c_zer64.v/alt_ntrlkn_12l_6g_crc32c_zer64_factor.v/alt_ntrlkn_12l_6g_crc32c_zer64_flat.v/alt_ntrlkn_12l_6g_dec_67_64.v/alt_ntrlkn_12l_6g_enc_64_67.v/alt_ntrlkn_12l_6g_fifo_36_to_72.v/alt_ntrlkn_12l_6g_fifo_72_to_36.v/alt_ntrlkn_12l_6g_frame_sync_control.v/alt_ntrlkn_12l_6g_gearbox_20_67.v/alt_ntrlkn_12l_6g_gearbox_67_20.v/alt_ntrlkn_12l_6g_hw.tcl/alt_ntrlkn_12l_6g_ilk_to_avalon_adapter_4.v/alt_ntrlkn_12l_6g_lal_cfifo.v/alt_ntrlkn_12l_6g_lal_dcfifo.v/alt_ntrlkn_12l_6g_lal_dfifo_auto.v/alt_ntrlkn_12l_6g_lane_alignment.v/alt_ntrlkn_12l_6g_lane_alignment_nav.v/alt_ntrlkn_12l_6g_lane_alignment_ram.v/alt_ntrlkn_12l_6g_lane_rx.v/alt_ntrlkn_12l_6g_lane_rx_crc.v/alt_ntrlkn_12l_6g_lane_status_monitor.v/alt_ntrlkn_12l_6g_lane_tx.v/alt_ntrlkn_12l_6g_lane_tx_crc.v/alt_ntrlkn_12l_6g_packet_annotate.v/alt_ntrlkn_12l_6g_packet_regroup_4.v/alt_ntrlkn_12l_6g_pipelined_any_flag.v/alt_ntrlkn_12l_6g_ram_navigate.v/alt_ntrlkn_12l_6g_read_calendar_4.v/alt_ntrlkn_12l_6g_read_calendar_single_page_4.v/alt_ntrlkn_12l_6g_read_scheduler_4.v/alt_ntrlkn_12l_6g_ready_skid.v/alt_ntrlkn_12l_6g_regroup_4.v/alt_ntrlkn_12l_6g_routing_pipe.v/alt_ntrlkn_12l_6g_rx_12lane.v/alt_ntrlkn_12l_6g_rx_buffer_fifo_2.v/alt_ntrlkn_12l_6g_rx_channel_filter_4.v/alt_ntrlkn_12l_6g_rx_crc24_check_4.v/alt_ntrlkn_12l_6g_rx_datapath_12lane.v/alt_ntrlkn_12l_6g_rx_stripe_adapter.v/alt_ntrlkn_12l_6g_scrambler_lfsr.v/alt_ntrlkn_12l_6g_sim_packet_client.v/alt_ntrlkn_12l_6g_six_three_comp.v/alt_ntrlkn_12l_6g_sum_of_3bit_pair.v/alt_ntrlkn_12l_6g_synchronizer.v/alt_ntrlkn_12l_6g_ternary_add.v/alt_ntrlkn_12l_6g_twelve_four_comp.v/alt_ntrlkn_12l_6g_tx_12lane.v/alt_ntrlkn_12l_6g_tx_2channel_arbiter.v/alt_ntrlkn_12l_6g_tx_4channel_arbiter.v/alt_ntrlkn_12l_6g_tx_buffer_fifo_8word.v/alt_ntrlkn_12l_6g_tx_buffer_fifo_nav.v/alt_ntrlkn_12l_6g_tx_buffer_fifo_ram.v/alt_ntrlkn_12l_6g_tx_buffer_fifo_ram_loose.v/alt_ntrlkn_12l_6g_tx_control_insertion_4.v/alt_ntrlkn_12l_6g_tx_crc24_insertion_4.v/alt_ntrlkn_12l_6g_tx_datapath_12lane.v/alt_ntrlkn_12l_6g_tx_flow_adapter.v/alt_ntrlkn_12l_6g_tx_stripe_adapter.v/alt_ntrlkn_12l_6g_wide_word_ram.v/alt_ntrlkn_12l_6g_wide_word_ram_4.v/alt_ntrlkn_12l_6g_word_align_control.v/alt_ntrlkn_12l_6g_xcvr_12lane.v/alt_ntrlkn_12l_6g_xor6.v/cadence/intelfpga/mentor/synopsys


filenames: address_decode_a10.qsys
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/ethernet/alt_em10g32/example_design/LL10G_10GBASER_RegMode/rtl/address_decoder


filenames: rtl
filetypes: d
dirname:
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filetypes: ffffffff
dirname:
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filenames:
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filenames: eth_100g_a10.qpf/eth_100g_a10.qsf/eth_100g_a10.sdc/eth_100g_a10.v
filetypes: ffff
dirname:
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filetypes: fffffffffffff
dirname:
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filenames:
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filetypes: ffffffffffffffffffffffffffffffffffffff
dirname:
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filenames:
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filenames: intel_pcie_cs.sv
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/intel_pcie/avmm_bridge_512/cs


filenames: common/hwtest/templates
filetypes: ddd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/ethernet/alt_e50s10/example_project


filenames: src_hdl
filetypes: d
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/vip/ip_library/common_hdl/modules/alt_vip_common_trigger_sync


filetypes: ffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/altera_uflex_interlaken/uflex_ilk_pcs/aldec

filenames:
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filetypes: fffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/dsp/altera_turbo/LTE/intelfpga/src/rtl/encoder

filenames:
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filenames: alt_vip_stream_cleaner_alg_core.sv
filetypes: f
dirname:
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filenames: dp_core.tcl.terp/dp_rx.tcl.terp/dp_tx.tcl.terp/edid_memory.hex
filetypes: ffff
dirname:
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filetypes: fffffffffffffffffffffffffffffff
dirname:
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filenames:
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filetypes: ffffffffffffffffffffffffffffffffff
dirname:
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filenames:
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filenames: aldec/cadence/intel_pcie_ptile_ast.sv.terp/intelfpga/mentor/synopsys/virtio
filetypes: ddfdddd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/intel_pcie/ptile/avst/rtl_legacy


filetypes: ffffffffffffffffffffffff
dirname:
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filenames:
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filenames: full_chip/sector_level
filetypes: dd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/asic_emu/intel_rdbk_wrbk/mentor


filenames: dp_core.tcl.terp/dp_rx.tcl.terp/dp_tx.tcl.terp/edid_memory.hex
filetypes: ffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/altera_dp/de_gen/arria_10/simulation/core


filenames: jtag_basic.tcl/main.tcl/report.tcl
filetypes: fff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/ethernet/alt_e40emu/example_project/hwtest/common


filenames: alt_e100_tx_e10x10_base.v
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/alt_eth_40g_100g/100gbe/rtl_src/phy/mentor/pma_siv/alt_e100_tx_e10x10


filenames: apn_fftfp_dft4_hdfp.vhd/apn_fftfp_fft4_hdfp.vhd
filetypes: ff
dirname:
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filetypes: ffffffff
dirname:
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filenames:
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filetypes: fffffffffffffffffffffffffffffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/vip/ip_library/full_ip/clocked_video_output/src_hdl

filenames:
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filenames: src_hdl
filetypes: d
dirname:
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filenames: csr/efc/mac/pcs/top
filetypes: ddddd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/ethernet/alt_e2550/25g/cadence/rtl


filetypes: fffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/ethernet/tse_ucores/altera_eth_tse_nf_lvds_terminator/cadence

filenames:
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filenames: altera_eth_addr_swapper.v
filetypes: f
dirname:
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filenames: src_hdl
filetypes: d
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/audio_ip/clocked_audio_input/mentor


filetypes: ffffffffffffffffffffff
dirname:
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filenames:
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filetypes: fffffffffffffffffffffffffffffffffffff
dirname:
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filenames:
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filetypes: fffffffffffffffffffff
dirname:
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filenames:
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filetypes: ffffffffff
dirname:
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filenames:
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filenames: ptile_pciecv_cii_workaround.v
filetypes: f
dirname:
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filetypes: ffffdfdfd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/altera_phylite/ip_s20_cfg_ctrl

filenames:
  altera_phylite_s20_cfg_ctrl_hw.tcl/common_gui.properties/common_messages.properties/gui.properties/intelfpga/main.tcl/mentor/messages.properties/rtl


filenames: src_hdl
filetypes: d
dirname:
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filenames: intel_vvp_round_sat_algo_comp.sv
filetypes: f
dirname:
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filenames: altpciexpav_lite_app.v
filetypes: f
dirname:
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filenames: det_lat/efifo/ls_pcs
filetypes: ddd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/cpriphy/alt_cpriphy_c3/mentor/rtl


filenames: altera_eth_tse_ftile_phyip_terminator.v
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/ethernet/tse_ucores/altera_eth_tse_ftile_phyip_terminator/synopsys


filenames: altera_eth_pfc_pause_conversion.v
filetypes: f
dirname:
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filenames: intel_vvp_crs_h_cmd_gen.sv
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/vvp/component_library/tcl_components/schedulers/intel_vvp_crs_h_cmd_gen/src_hdl


filetypes: ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/ethernet/alt_mge_phy/aldec/rtl

filenames:
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filenames: aldec/cadence/intel_vvp_vvp_to_message_conv_hw.tcl/intelfpga/mentor/src_hdl/synopsys
filetypes: ddfdddd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/vvp/component_library/tcl_components/legacy/intel_vvp_vvp_to_message_conv


filetypes: fffffffffffffffffffffff
dirname:
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filenames:
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filenames: intel_vvp_tmo_io.h
filetypes: f
dirname:
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filenames: alt_ntrlkn_oob_flow_rx.v/alt_ntrlkn_oob_flow_rx_dcfifo.v
filetypes: ff
dirname:
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filetypes: ddfffddd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/altera_hdmi/src/phy_intf/tx

filenames:
  aldec/cadence/intel_hdmi_ce.v/intel_hdmi_tx_core_phy_intf.v/intel_hdmi_tx_oversample.v/intelfpga/mentor/synopsys


filetypes: fff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/ethernet/alt_em10g32/MAC/intelfpga/adapters/altera_eth_xgmii_data_format_adapter

filenames:
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filenames: 10g_mac_reg_map.tcl/mac_inc.tcl
filetypes: ff
dirname:
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filetypes: fffffffffffffffffff
dirname:
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filenames:
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filenames: altera_10gbaser_phy_clockcomp.sv/altera_10gbaser_phy_rx_fifo.sv/altera_10gbaser_phy_soft_fifo.v
filetypes: fff
dirname:
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filetypes: dffd
dirname:
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filenames:
[cell repeats an earlier one in this file: 120 characters]


filenames: src_hdl
filetypes: d
dirname:
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filetypes: fffff
dirname:
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filenames:
[cell repeats an earlier one in this file: 176 characters]


filenames: mem_ss_reset_sim_source.sv
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/subsystems/mem_ss/ip_reset_sim_source/rtl


filetypes: fffffffffffffff
dirname:
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filenames:
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filetypes: ffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/vvp/component_library/tcl_components/schedulers/intel_vvp_vfb_scheduler/mentor/src_hdl

filenames:
  intel_vvp_vfb_scheduler.sv/intel_vvp_vfb_scheduler_buff_num.sv/intel_vvp_vfb_scheduler_rd.sv/intel_vvp_vfb_scheduler_wr.sv


filenames: aldec/alt_vip_warp_line_store_hw.tcl/cadence/intelfpga/mentor/src_hdl/synopsys
filetypes: dfddddd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/vip/ip_library/component_ip/utility/alt_vip_warp_line_store


filenames: src_hdl
filetypes: d
dirname:
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filetypes: fffffffffffffffffffffffffffffffffffffd
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filenames:
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filenames: alt_e40_gray_to_bin.v/alt_e40_mlab_dcfifo.v/alt_e40_mlab_fifo_cells.v/alt_e40_random_delay.v
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filenames: verilog
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filenames: src_hdl
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filetypes: fffffffffffffffffffffffffffffffffffffffffffffffffff
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filenames: rtl
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filenames:
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filenames: core/pkg
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filenames: alt_vip_dil_algorithm.sv
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filetypes: ffff
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filenames: alt_vip_cpp_converter.sv
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filenames: verilog/vhdl
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filenames: drc_pkg.sv/responder_core.sv/responder_core_fm_top.sv/switch_scfifo.sv
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filenames: intel_vvp_mm_agent_reset_hold.sv
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filenames: src_hdl
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filetypes: ffffffffff
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filenames:
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filenames: marvell_phy_reg_map.tcl/sfpp_i2c.tcl
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filenames: full_chip/sector_level
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filenames: src_hdl
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filenames: example_project/rtl
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filetypes: fffffffffffffffffffffffffff
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filenames:
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filetypes: fffffffffffffffffffffff
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filenames:
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filenames: intel_pcie_pipestage.sv
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filenames: avalonstloopback/gen/mon/traffic_controller.tcl
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filenames: phylite_s10_sim_ctrl.sv
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filenames: det_lat/efifo/ls_pcs
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dirname:
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filenames: alt_e100_phy_pma_sv.v
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filetypes: ffff
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filenames:
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filenames: alt_aeu_100_efc_top.v/alt_aeu_100_sfc_top.v
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filetypes: ffdfffffffff
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filetypes: ffffffffff
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filenames:
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filenames: hps_periphs.tcl
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filetypes: dddd
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filenames:
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filenames: alt_vip_common_stream_output.sv
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filetypes: ffff
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filenames:
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filetypes: ffff
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filenames:
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filenames: system_console/system_console_fm
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filenames: Makefile.txt/latency/sapp.c
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filenames: src_hdl
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filenames: BackPlane_wo_1588.qprs/LineSide.qprs/LineSide_1588.qprs
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filenames: intel_hdmi_edid_hdlg.v/intel_hdmi_hpd_hdlg.v/intel_hdmi_ltp_chk.v
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filenames: altera_eth_preamble_custom.v
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filetypes: ffff
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filenames:
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filetypes: fffffff
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filenames:
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filenames: intel_vvp_vvp_to_message_conv.sv/intel_vvp_vvp_to_message_conv_ctrl.sv
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filenames: run_vcs.sh/run_vcsmx.sh
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filenames: intel_vvp_csc_scheduler.sv
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filenames: tod_inc.tcl/tod_reg_map.tcl
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filenames: tb_run.tcl/wave.do
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dirname:
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filenames: build_sw.sh/build_sw_hdcp.sh
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filenames:
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filetypes: ffffff
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filenames:
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filetypes: dfdfdffdd
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filenames:
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filetypes: dfffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffddd
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filenames:
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filenames: altera_external_memory_bfm.sv/altera_external_memory_bfm_vhdl_wrapper.sv
filetypes: ff
dirname:
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filenames: src_hdl
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dirname:
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filetypes: ffffff
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filenames:
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filenames: src_hdl
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dirname:
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filenames: intel_pcie_lite_bas.sv/intel_pcie_mcdma_bas.sv/intel_pcie_mcdma_bas_wrapper.v
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filetypes: dffdddd
dirname:
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filenames:
  aldec/altera_eth_avst2gmii_converter.v/altera_eth_avst2gmii_converter_hw.tcl/cadence/intelfpga/mentor/synopsys


filenames: alt_vip_common_dc_mixed_widths_fifo.sv
filetypes: f
dirname:
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filenames: src_hdl
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filenames: intel_vvp_crs_v_cmd_gen.sv
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dirname:
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filetypes: fffffffffffffffffffffffffffffffffffffffffffffffffff
dirname:
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filenames:
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filetypes: fffffffffffffffffffffffff
dirname:
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filenames:
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filenames: core/pkg
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dirname:
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filetypes: fffffffffffff
dirname:
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filenames:
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filetypes: ffffffff
dirname:
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filenames:
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filenames: src_hdl
filetypes: d
dirname:
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filetypes: fffffffffff
dirname:
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filenames:
  intel_vvp_3d_lut_addr_decode.sv/intel_vvp_3d_lut_avlmm_if.sv/intel_vvp_3d_lut_axis_shim.sv/intel_vvp_3d_lut_config.sv/intel_vvp_3d_lut_cpu_bridge.sv/intel_vvp_3d_lut_ctrl_if.sv/intel_vvp_3d_lut_dsp.sv/intel_vvp_3d_lut_interp_tetra.sv/intel_vvp_3d_lut_ram_proc_if.sv/intel_vvp_3d_lut_switch.sv/intel_vvp_3d_lut_top.sv


filenames: intel_vvp_axi_st_pipe_bridge.sv
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dirname:
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filenames: src_hdl
filetypes: d
dirname:
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filenames: virtio
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dirname:
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filetypes: dfffdddddd
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filenames:
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filenames: altera_ldpc_dvb_enc.sv/altera_ldpc_dvb_enc_mat.sv
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filenames: alt_e40_mac_addr_regs.v/alt_e40_mac_csr.v/alt_e40_status_cntr_pause_sync.v
filetypes: fff
dirname:
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filetypes: fffffffffffffff
dirname:
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filenames:
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filenames: nios_system
filetypes: d
dirname:
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filenames: altera_xcvr_pll_av_wizard.lst/pkgIndex.tcl/tcl
filetypes: ffd
dirname:
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filetypes: fffffffffffffffffffffffffffff
dirname:
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filenames:
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filetypes: ffffffff
dirname:
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filenames:
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filenames: common
filetypes: d
dirname:
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filenames: altera_eth_mdio.v
filetypes: f
dirname:
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filenames: src_hdl
filetypes: d
dirname:
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filenames: csr/efc/kr/mac/pcs/top
filetypes: dddddd
dirname:
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filetypes: ffffffff
dirname:
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filenames:
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filenames: alt_vip_video_output_bridge.ocp/alt_vip_video_output_bridge.sv
filetypes: ff
dirname:
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filenames: alt_e50s10_kr_rcfg_arb.sv/alt_e50s10_reco_arbiter.v/alt_e50s10_resync_nocut.sv
filetypes: fff
dirname:
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filenames: altera_eth_avst2gmii_converter.v
filetypes: f
dirname:
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filenames: src_hdl
filetypes: d
dirname:
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filetypes: fffff
dirname:
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filenames:
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filenames: src_hdl
filetypes: d
dirname:
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filenames: aldec/cadence/intel_vvp_fifo_core_hw.tcl/intelfpga/mentor/src_hdl/synopsys
filetypes: ddfdddd
dirname:
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filenames: altera_dib_arch_aux.sv/altera_dib_arch_aux_bufs.sv/altera_dib_arch_aux_io_wrp.sv
filetypes: fff
dirname:
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filetypes: ffffffffff
dirname:
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filenames:
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filetypes: fffffffffffffffffffffffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/subsystems/pcie_ss/rtl/cadence/data_mover

filenames:
  pciess_cpl_metering.sv/pciess_dm_2r2w_mem.sv/pciess_dm_c2h_arbiter.sv/pciess_dm_c2h_bs.v/pciess_dm_c2h_flr_chk.sv/pciess_dm_c2h_rtlpf.sv/pciess_dm_c2h_top.sv/pciess_dm_c2h_wtlpf.v/pciess_dm_c2h_wtlpf_data_split.sv/pciess_dm_c2h_wtlpf_hdr.sv/pciess_dm_completion_tracker.sv/pciess_dm_data_pipeline.v/pciess_dm_devatt.sv/pciess_dm_flr_if.sv/pciess_dm_h2c_cpl_hdr_buffer.sv/pciess_dm_h2c_cpl_pending_array.sv/pciess_dm_h2c_cpl_reordering.sv/pciess_dm_h2c_cpl_split_tracking.sv/pciess_dm_h2c_find_free_addr.sv/pciess_dm_h2c_flr_chk.sv/pciess_dm_h2c_free_addr_tracking.sv/pciess_dm_h2c_mem_1r1w_ram.v/pciess_dm_h2c_packer.sv/pciess_dm_h2c_req_tracking.sv/pciess_dm_h2c_tlp_hdr_reformatting.sv/pciess_dm_h2c_top.v/pciess_dm_lite_csr_router.sv/pciess_dm_sort_arb.sv/pciess_dm_vf_err_msg.sv


filenames: altera_mailbox_avalonst_fifo.sv
filetypes: f
dirname:
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filenames: vcs
filetypes: d
dirname:
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filenames: avalon_st_loopback_inc.tcl/avalon_st_loopback_reg_map.tcl
filetypes: ff
dirname:
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filetypes: fffffffd
dirname:
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filenames:
  ifc_libmcmem.h/ifc_libmqdma.h/ifc_mcdma.h/ifc_qdma_utils.h/ifc_reglib_osdep.h/ifc_status.h/mcdma_ip_params.h.terp/regs


filetypes: fffff
dirname:
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filenames:
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filetypes: fffffffffffffffff
dirname:
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filenames:
  intel_vvp_3d_lut_pkg.sv/intel_vvp_clipper_pkg.sv/intel_vvp_common_pkg.sv/intel_vvp_crs_pkg.sv/intel_vvp_csc_pkg.sv/intel_vvp_guard_bands_pkg.sv/intel_vvp_mixer_pkg.sv/intel_vvp_mpvdma_pkg.sv/intel_vvp_pip_conv_pkg.sv/intel_vvp_protocol_conv_pkg.sv/intel_vvp_scaler_pkg.sv/intel_vvp_snoop_pkg.sv/intel_vvp_tmo_pkg.sv/intel_vvp_tpg_pkg.sv/intel_vvp_utility_pkg.sv/intel_vvp_vfb_pkg.sv/intel_vvp_warp_pkg.sv


filetypes: ffffddd
dirname:
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filenames:
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filenames: altera_eth_preamble_inserter.v
filetypes: f
dirname:
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filetypes: dfdfd
dirname:
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filenames:
[cell repeats an earlier one in this file: 114 characters]


filenames: j204c_rx_regmap.v
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filenames:
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filenames: altera_up_avalon_video_vga_controller.v/altera_up_avalon_video_vga_timing.v
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filenames: main.tcl.terp
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filenames: rnr_avmm_reconfig.sv/rnr_pipe_direct_rate_change_control.sv/rnr_rate_change_control.sv
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filenames: altera_eth_packet_underflow_control.v
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filenames:
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filenames: altera_nios2_custom_instr_slave_bfm_vhdl.vhd/altera_nios2_custom_instr_slave_bfm_vhdl_pkg.vhd
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filenames:
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filetypes: ffffff
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filenames:
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filenames: src_hdl
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filenames:
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filenames: aldec/alt_vip_control_slave_hw.tcl/cadence/intelfpga/mentor/src_hdl/synopsys
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filetypes: ffffff
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filenames:
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filetypes: fffffdfdd
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filenames:
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filenames: src_hdl
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filenames: alt_mlab.v
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filenames: alt_vip_common_fifo2.sv
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filetypes: fffffffffffdffffff
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filenames:
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filenames: src_hdl
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filenames:
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filenames: alt_vip_mixer_alpha_merge.sv
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dirname:
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filenames: src_hdl
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dirname:
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filetypes: fffff
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filenames:
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filetypes: ffffffffffffffff
dirname:
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filenames:
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filenames: src_hdl
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filetypes: ffffffffff
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filenames:
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filenames: alt_vip_warp_ac.ocp/alt_vip_warp_ac.sv/alt_vip_warp_bilinear_ac.sv
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dirname:
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filenames: llr_CR=1by3_Z=384_BG1.orig.txt/llr_CR=1by3_Z=384_BG1.txt/msg_CR=1by3_Z=384_BG1.txt
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filenames: alt_e40_jtag_avmm.v/alt_e40_reset_controller.v
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filenames: intel_vvp_pip_conv_core.sv
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filenames: src_hdl
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filenames: axilite2avmm/csr/pciess_lite_csr_router.sv/pciess_lite_csr_termination.sv/pciess_lite_mstr2slv.sv
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filenames:
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filenames: altera_sl3_phy_adapter.sv/altera_sl3_phy_adapter_c3.sv
filetypes: ff
dirname:
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filetypes: dffffffdddd
dirname:
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filenames:
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filetypes: fffffffffffffff
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filenames:
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filenames: intel_pcie_pipestage.sv
filetypes: f
dirname:
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filenames: sv_xcvr_att_custom_native.sv
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dirname:
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filetypes: ffffffffffffffffff
dirname:
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filenames:
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filetypes: fffffffffffffff
dirname:
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filenames:
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filenames: alt_aeu_40/kr4/optical_module/pkt_client/sval_top
filetypes: ddddd
dirname:
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filetypes: ffff
dirname:
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filenames:
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filenames: src_hdl
filetypes: d
dirname:
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filenames: alt_e40_jtag_avmm.v/alt_e40_rcfg_arb.sv/alt_e40_reset_controller.v
filetypes: fff
dirname:
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filenames: fifo_inc.tcl/fifo_reg_map.tcl
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dirname:
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filenames: aldec/alt_vip_clipper_scheduler_hw.tcl/cadence/intelfpga/mentor/src_hdl/synopsys
filetypes: dfddddd
dirname:
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filenames: alt_e40_phy_pcs.v/common/rx/tx
filetypes: fddd
dirname:
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filetypes: fffff
dirname:
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filenames:
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filenames: rtile_sriov_ed_top.sv
filetypes: f
dirname:
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filenames: altera_eth_tse_bridge.v
filetypes: f
dirname:
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filenames: alt_e40_jtag_avmm.v/alt_e40_rcfg_arb.sv/alt_e40_reset_controller.v
filetypes: fff
dirname:
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filetypes: ffffffffffffffff
dirname:
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filenames:
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filenames: address_decoder_top_altera_merlin_slave_translator_191_x56fcki.sv
filetypes: f
dirname:
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filetypes: fffffffffffffffffffffffff
dirname:
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filenames:
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filenames: address_decoder_multi_channel.qsys/address_decoder_top.qsys/ip/mch/top
filetypes: ffddd
dirname:
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filetypes: dddd
dirname:
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filenames:
[cell repeats an earlier one in this file: 125 characters]


filetypes: dfffffffdf
dirname:
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filenames:
[cell repeats an earlier one in this file: 335 characters]


filetypes: ffffdd
dirname:
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filenames:
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filenames: src_hdl
filetypes: d
dirname:
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filetypes: fff
dirname:
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filenames:
[cell repeats an earlier one in this file: 103 characters]


filetypes: ffffffffff
dirname:
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filenames:
[cell repeats an earlier one in this file: 246 characters]


filenames: altera_avalon_sysid.h
filetypes: f
dirname:
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filenames: ilk_8l_6g_rx_stripe_adapter.v/ilk_8l_6g_tx_stripe_adapter.v
filetypes: ff
dirname:
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filenames: src_hdl
filetypes: d
dirname:
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filetypes: fffffffffffffffff
dirname:
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filenames:
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filetypes: fffffffffffffffffff
dirname:
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filenames:
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filenames: rx/top/tx
filetypes: ddd
dirname:
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filetypes: fffffffff
dirname:
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filenames:
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filenames: tb_run.sh/xcelium_wave.tcl
filetypes: ff
dirname:
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filetypes: fffffffff
dirname:
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filenames:
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filenames: alt_aeu_40/kr4/optical_module/pkt_client/sval_top
filetypes: ddddd
dirname:
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filenames: pkgIndex.tcl/tcl
filetypes: fd
dirname:
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filetypes: ffffff
dirname:
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filenames:
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filetypes: ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
dirname:
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filenames:
[cell repeats an earlier one in this file: 2284 characters]


filetypes: fff
dirname:
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filenames:
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filenames: altera_external_memory_bfm.sv/altera_external_memory_bfm_vhdl_wrapper.sv
filetypes: ff
dirname:
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filenames: altera_avalon_altpll_hw.tcl
filetypes: f
dirname:
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filetypes: ffffff
dirname:
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filenames:
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filetypes: ffff
dirname:
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filenames:
[cell repeats an earlier one in this file: 115 characters]


filenames: j204c_rx_regmap.v
filetypes: f
dirname:
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filetypes: fffff
dirname:
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filenames:
[cell repeats an earlier one in this file: 160 characters]


filetypes: fffff
dirname:
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filenames:
[cell repeats an earlier one in this file: 100 characters]


filetypes: fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/altera_dp/src/mentor/displayport2p0/rx

filenames:
  dp1p4_rx_decoder.v/dp1p4_rx_phy_word_aligner.sv/dp2p0_rx_crc_checker.sv/dp2p0_rx_decoder.sv/dp2p0_rx_ll.sv/dp2p0_rx_ll_control.sv/dp2p0_rx_ll_decoder.sv/dp2p0_rx_ll_decoder_audio.sv/dp2p0_rx_ll_decoder_msa.sv/dp2p0_rx_ll_decoder_sdp.sv/dp2p0_rx_ll_decoder_sym_packer.sv/dp2p0_rx_ll_decoder_vbid.sv/dp2p0_rx_ll_demux.sv/dp2p0_rx_ll_demux_llcp.sv/dp2p0_rx_ll_demux_mtp.sv/dp2p0_rx_ll_pixel_crc.sv/dp2p0_rx_ll_pr.sv/dp2p0_rx_ll_vid.sv/dp2p0_rx_lphy.sv/dp2p0_rx_lphy_ber_cnt.sv/dp2p0_rx_lphy_cdi4.sv/dp2p0_rx_lphy_descrambler.sv/dp2p0_rx_lphy_lane_converter.sv/dp2p0_rx_lphy_lane_converter_setup.sv/dp2p0_rx_lphy_lane_converter_sym_packer.sv/dp2p0_rx_lphy_lt_ctrl.sv/dp2p0_rx_lphy_prbs_checker.sv/dp2p0_rx_lphy_precoding.sv/dp2p0_rx_lphy_symbol_deshifting.sv/dp2p0_rx_lphy_symbol_deshifting_maj_4b.sv/dp2p0_rx_lphy_sync_patt_detect.sv/dp2p0_rx_lphy_video_decode.sv/dp2p0_rx_lphy_video_decode_cdi1_1spc_1lane.sv/dp2p0_rx_lphy_video_decode_cdi1_1spc_2lane.sv/dp2p0_rx_lphy_video_decode_cdi1_24_1_mux.sv/dp2p0_rx_lphy_video_decode_cdi1_2spc_1lane.sv/dp2p0_rx_lphy_video_decode_cdi1_2spc_2lane.sv/dp2p0_rx_lphy_video_decode_cdi1_48_1_mux.sv/dp2p0_rx_lphy_video_decode_control.sv/dp2p0_rx_lphy_video_decode_downshift.sv/dp2p0_rx_lphy_video_decode_downshift_lane0.sv/dp2p0_rx_lphy_video_decode_fec_error.sv/dp2p0_rx_lphy_video_decode_fec_error_bit_counter.sv/dp2p0_rx_lphy_video_decode_fec_error_block_counter.sv/dp2p0_rx_lphy_video_decode_fec_error_block_increment.sv/dp2p0_rx_lphy_video_decode_fec_error_lane.sv/dp2p0_rx_lphy_video_decode_fec_in_mux.sv/dp2p0_rx_lphy_video_decode_fec_rst_gen.sv/dp2p0_rx_lphy_video_decode_fec_rst_iso.sv/dp2p0_rx_lphy_video_decode_out_symbol_shifter.sv/dp2p0_rx_lphy_video_decode_phy_sync_check.sv/dp2p0_rx_lphy_video_decode_sym_ram_in_mux.sv/dp2p0_rx_lphy_video_decode_sync_loss.sv/dp2p0_rx_lphy_video_decode_upshift.sv/dp2p0_rx_lphy_video_decode_upshift_lane0.sv/dp2p0_rx_lphy_video_decode_word_deinterleave_1spc_1lane.sv/dp2p0_rx_lphy_video_decode_word_deinterleave_2spc_1lane.sv/dp2p0_rx_lphy_video_decode_word_interleave.sv/dp2p0_rx_lphy_video_decode_word_interleave_1spc_1lane.sv/dp2p0_rx_lphy_video_decode_word_interleave_2spc_1lane.sv/dp2p0_rx_lphy_video_decode_word_shifter.sv/dp2p0_rx_reg_ctrl.sv/dp2p0_rx_reg_ctrl_fec_mux.sv/dp2p0_rx_reset_ctrl.sv/dp2p0_rx_rst_ctrl.sv/dp2p0_rx_sync_loss_hysteresis.sv/dp2p0_rx_video_stream.sv/dp_rx_aux_ctrl.sv/dp_rx_decoder_top.sv/fec_decoder


filenames: lpddr4_pmu_train_dmem.incv/lpddr4_pmu_train_imem.incv
filetypes: ff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/intel_hps/dm/ddr/synopsys_fw/a-2018.10/lpddr4


filetypes: ffffffffffffffffffffffffffffffffffffffffffffffffff
dirname:
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filenames:
[cell repeats an earlier one in this file: 1527 characters]


filenames: src_hdl
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filenames: alt_vip_dil_low_angle_algorithm.sv/alt_vip_dil_pixel_offset_rom.v
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filetypes: ffff
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filenames: alt_vip_pip_converter_core.sv
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filenames: src_hdl
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filenames: mainband/pcie_adapter_top.sv/pcie_synchronizer_pulse.sv/pcie_synchronizer_vec.sv/sideband
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filenames: alt_vip_common_mult_add_nodsp.sv
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filenames: src_hdl
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filenames: ddr4_pmu_train_dmem.incv/ddr4_pmu_train_imem.incv
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filetypes: fffffffffffffffffffffffff
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filenames: common.txt/env.txt
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filetypes: ffffffd
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filenames:
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filenames: cfp_control_inc.tcl/main.tcl/qsfp_control_inc.tcl
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filenames: altera_generic_quad_spi_controller2_regs.h
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dirname:
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filenames: intel_vvp_reset_sync.sdc/intel_vvp_reset_sync.sv
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filenames: alt_e100_sys_pll_siv.qip/alt_e100_sys_pll_siv.v
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filenames:
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filenames: spiphyslave.sdc/spiphyslave.v/spiphyslave_hw.tcl
filetypes: fff
dirname:
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filetypes: ffffffffff
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filenames:
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dirname:
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filenames:
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filetypes:
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filetypes: ffffffddf
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filenames: src_hdl
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filetypes: fffffffffffffffff
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filenames:
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filenames: alt_vip_video_input_bridge_cmd.sv
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filenames: alt_ehipc3_fm_sl_avmm_rcfg_hw.tcl
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dirname:
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filenames: intel_vvp_pkt_mux.sv
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filenames: aldec/c_model/cadence/intelfpga/matlab/mentor/rtl/spyglass/synopsys
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filenames: alt_mlab.v
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filetypes: ffff
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filenames:
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filenames: alt_ehipc2_alias_csr.sv/alt_ehipc2_avmm_32to8.sv/alt_ehipc2_csr.v
filetypes: fff
dirname:
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filenames: altera_avalon_lan91c111_regs.h
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dirname:
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filenames: example_project/rtl
filetypes: dd
dirname:
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filenames: mif/mr_compare_threshold_rxphy.sv/mr_rxphy.qip/rcfg_array_streamer_rxphy_incl.sv
filetypes: dfff
dirname:
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filenames: alt_vip_common_stream_input.v
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dirname:
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filenames: ftile_cpri_test.tcl/ftile_elane_xcvr_loopback_test.tcl
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dirname:
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filenames: alt_ehipc2_rx_deskew.sv/alt_ehipc2_tx_deskew.sv/alt_ehipc2_word_delay_mlab.sv
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filenames: altera_eth_link_fault_generation_unidirectional.v
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dirname:
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filetypes: dfdddfffffffffffffffffffffffffffd
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filenames:
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filetypes: ffffffff
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filenames:
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filenames: eth_f_package.sv
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dirname:
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filenames: dp2p0_txll_vsc.sv/dp2p0_txll_vsc_top.sv
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dirname:
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filetypes: dfffddddddffdd
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filenames:
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filetypes: ffffffffffff
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filenames:
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filetypes: fffffff
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filenames:
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filenames: alt_vip_packet_duplicator.sv
filetypes: f
dirname:
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filenames: intel_vvp_msg_to_axi.sv
filetypes: f
dirname:
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filenames: alt_e50s10_adapt_pma.v/alt_e50s10_eli_jtag.v/alt_e50s10_pll_recal.v/alt_e50s10_reset_controller.v
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dirname:
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filenames: src_hdl
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dirname:
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filetypes: fffffffffffffffffffffffffff
dirname:
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filenames:
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filenames: intel_cv2axi_hw.tcl/sw
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dirname:
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filetypes: fffffffffffffffffffffffffffffffffffffffffffffffffff
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filenames:
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filetypes: fdfffffffffffffffffffffffffffffffffffffffff
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filenames:
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filenames: altera_avalon_transacto.sv/altera_avalon_transacto_hw.tcl
filetypes: ff
dirname:
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filenames: rtl
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dirname:
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filenames: clock_crosser.v/dcfifo_inst.v.terp/debouncer.sv/fifo.tcl.terp/output_buf_i2c.tcl.terp
filetypes: fffff
dirname:
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filenames: adapter_common
filetypes: d
dirname:
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filenames: altera_eth_pause_controller.v/altera_eth_pause_ctrl_gen.v/altera_eth_pause_gen.v
filetypes: fff
dirname:
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filetypes: ffffffffffffffffffffff
dirname:
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filenames:
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filenames: 10g_mac_reg_map.tcl/mac_inc.tcl
filetypes: ff
dirname:
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filenames: src_hdl
filetypes: d
dirname:
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filenames: wirelist.net
filetypes: f
dirname:
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filenames: src_hdl
filetypes: d
dirname:
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filenames: src_hdl
filetypes: d
dirname:
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filetypes: ffffffffffffffffffffffffffffffffffffffffffffffffff
dirname:
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filenames:
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filenames: intel_pcie_baselimit_compare.sv
filetypes: f
dirname:
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filenames: alt_vip_cl_packet_dangler.sv
filetypes: f
dirname:
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filenames: altera_jtag_debug_link_hw.tcl/altera_jtag_debug_link_internal_hw.tcl
filetypes: ff
dirname:
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filetypes: ffffffffffff
dirname:
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filenames:
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filenames: alt_interlaken_pcs_siv_hw.tcl
filetypes: f
dirname:
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filenames: altera_avalon_mailbox_simple.h
filetypes: f
dirname:
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filetypes: ffffffff
dirname:
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filenames:
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filenames: aldec/cadence/intel_vvp_csc_scheduler_hw.tcl/intelfpga/mentor/src_hdl/synopsys
filetypes: ddfdddd
dirname:
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filenames: alt_e40_adapter.v/alt_e40_wide_l2if_rx_mux.v/alt_e40_wide_l2if_tx.v
filetypes: fff
dirname:
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filenames: alt_vip_tpg_multi_scheduler.sv
filetypes: f
dirname:
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filetypes: fffffffffffff
dirname:
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filenames:
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filetypes: ffffffffff
dirname:
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filenames:
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filetypes: ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffdf
dirname:
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filenames:
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filenames: src_hdl
filetypes: d
dirname:
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filenames: ast2avmm_bridge_256_hwtcl.sv
filetypes: f
dirname:
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filenames: bchp_syndrome.vhd/bchp_syndromes_sqr.vhd
filetypes: ff
dirname:
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filenames: rx/top/tx
filetypes: ddd
dirname:
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filenames: auk_dspip_r22sdf_lib_pkg.vhd
filetypes: f
dirname:
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filetypes: ffffffffffffffff
dirname:
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filenames:
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filenames: altera_generic_quad_spi_controller.h
filetypes: f
dirname:
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filenames: src_hdl
filetypes: d
dirname:
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filenames: alt_a10mlab.v/alt_wys_lut.v
filetypes: ff
dirname:
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filetypes: ffffffffffffffffffffffffffffffffffff
dirname:
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filenames:
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filenames: rx/top/tx
filetypes: ddd
dirname:
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filenames: altera_customins_xconnect.sv.terp/altera_customins_xconnect_hw.tcl
filetypes: ff
dirname:
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filenames: altera_voltage_sensor_control.sv/voltage_sensor_avalon_control.sv/voltage_sensor_wrapper.sv
filetypes: fff
dirname:
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filenames: src_hdl
filetypes: d
dirname:
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filetypes: ffff
dirname:
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filenames:
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filetypes: ddffddd
dirname:
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filenames:
  aldec/cadence/intel_vab_common_slave_interface.sv/intel_vab_ext_interlace_toggle.sv/intelfpga/mentor/synopsys


filenames: phy_ip_inc.tcl/phy_ip_reg_map.tcl
filetypes: ff
dirname:
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filenames: ptile_pciecv_cii_workaround.v
filetypes: f
dirname:
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filenames: alt_vip_bps_converter.sv
filetypes: f
dirname:
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filenames: issp.tcl/kr4.tcl/kr4_ml.tcl/kr_lpbk.tcl/main.tcl/main_ml.tcl
filetypes: ffffff
dirname:
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filenames: intel_lvds_common10.sv
filetypes: f
dirname:
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filenames: altera_mbox_data_adapter.sv/altera_mbox_data_adapter_hw.tcl
filetypes: ff
dirname:
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filenames: inc/intel_vvp_scaler_sw.tcl/src
filetypes: dfd
dirname:
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filenames: src_hdl
filetypes: d
dirname:
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filenames: sv_xcvr_data_mapper.sv
filetypes: f
dirname:
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filetypes: fffffffffffffffffffffffffffff
dirname:
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filenames:
  pciess_cpl_metering.sv/pciess_dm_2r2w_mem.sv/pciess_dm_c2h_arbiter.sv/pciess_dm_c2h_bs.v/pciess_dm_c2h_flr_chk.sv/pciess_dm_c2h_rtlpf.sv/pciess_dm_c2h_top.sv/pciess_dm_c2h_wtlpf.v/pciess_dm_c2h_wtlpf_data_split.sv/pciess_dm_c2h_wtlpf_hdr.sv/pciess_dm_completion_tracker.sv/pciess_dm_data_pipeline.v/pciess_dm_devatt.sv/pciess_dm_flr_if.sv/pciess_dm_h2c_cpl_hdr_buffer.sv/pciess_dm_h2c_cpl_pending_array.sv/pciess_dm_h2c_cpl_reordering.sv/pciess_dm_h2c_cpl_split_tracking.sv/pciess_dm_h2c_find_free_addr.sv/pciess_dm_h2c_flr_chk.sv/pciess_dm_h2c_free_addr_tracking.sv/pciess_dm_h2c_mem_1r1w_ram.v/pciess_dm_h2c_packer.sv/pciess_dm_h2c_req_tracking.sv/pciess_dm_h2c_tlp_hdr_reformatting.sv/pciess_dm_h2c_top.v/pciess_dm_lite_csr_router.sv/pciess_dm_sort_arb.sv/pciess_dm_vf_err_msg.sv


filenames: alt_vip_common_seq_par_convert.sv
filetypes: f
dirname:
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filetypes: ffffffffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/soft_processor/intel_niosv_m/cadence

filenames:
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filenames: alt_vip_cl_guard_bands_hw.tcl
filetypes: f
dirname:
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filenames: intel_vvp_warp_r2b.sv
filetypes: f
dirname:
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filenames: src_hdl
filetypes: d
dirname:
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filetypes: fffffffff
dirname:
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filenames:
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filetypes: fffffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/altera_pcie/altera_pcie_s10_hip_avmm_bridge/mentor/altera_pcie_s10_readdatamover

filenames:
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filetypes: fffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/ilk/ftile/ilk_f_efifo/cadence

filenames:
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filetypes: fffff
dirname:
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filenames:
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filetypes: ffffff
dirname:
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filenames:
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filetypes: ffffffffffffffffffffffffffffff
dirname:
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filenames:
  intel_vvp_tmo_a10_sysdsp.sv/intel_vvp_tmo_ag_sysdsp.sv/intel_vvp_tmo_altsyncram.sv/intel_vvp_tmo_avlmm_if.sv/intel_vvp_tmo_axis_shim.sv/intel_vvp_tmo_c10_sysdsp.sv/intel_vvp_tmo_cpu_bridge.sv/intel_vvp_tmo_csa.sv/intel_vvp_tmo_datapath.sv/intel_vvp_tmo_dline.sv/intel_vvp_tmo_dsp.sv/intel_vvp_tmo_ext_add.sv/intel_vvp_tmo_ext_mult.sv/intel_vvp_tmo_heq.sv/intel_vvp_tmo_hgen.sv/intel_vvp_tmo_luma2rgb.sv/intel_vvp_tmo_lut.sv/intel_vvp_tmo_pdelay.sv/intel_vvp_tmo_regs.sv/intel_vvp_tmo_regs_external.sv/intel_vvp_tmo_regs_internal.sv/intel_vvp_tmo_rgb2luma.sv/intel_vvp_tmo_rmw.sv/intel_vvp_tmo_rmw_tile.sv/intel_vvp_tmo_roi.sv/intel_vvp_tmo_s10_sysdsp.sv/intel_vvp_tmo_sdpram.sv/intel_vvp_tmo_stream_formater.sv/intel_vvp_tmo_tready_reg.sv/intel_vvp_tmo_vid_monitor.sv


filenames: src_hdl
filetypes: d
dirname:
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dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/ethernet/alt_e40emu/hslx/cadence

filenames:
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filetypes:
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filenames: wd_timer_hw.tcl
filetypes: f
dirname:
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filetypes: fffffffff
dirname:
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filenames:
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filetypes: fffffffffffffffffffffffffffffffffffffffffffffffffff
dirname:
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filenames:
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filetypes: dfffdddd
dirname:
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filenames:
  aldec/altera_eth_packet_overflow_control.ocp/altera_eth_packet_overflow_control.v/altera_eth_packet_overflow_control_hw.tcl/cadence/intelfpga/mentor/synopsys


filetypes: fffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/altera_jesd204/src/rx_mlpcs/s10_16g/spyglass

filenames:
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filenames: altera_ldpc_pkg.sv
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/dsp/altera_ldpc/src/lib/aldec


filenames: src_hdl
filetypes: d
dirname:
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filenames: intel_vvp_pip_conv_core.sv
filetypes: f
dirname:
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filenames: rtl
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filetypes: fffffffffffffffffff
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filenames:
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filenames: altera_avalon_st_splitter.sv/altera_avalon_st_splitter_hw.tcl
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filenames: alt_mge_packet_classifier_s10.ip
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filenames: rx/top/tx
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filenames:
  intel_vvp_vert_scaler_algo_comp.sv/intel_vvp_vert_scaler_algo_comp_bl.sv/intel_vvp_vert_scaler_algo_comp_coeff.sv


filenames: src_hdl
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dirname:
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filetypes: fffffffff
dirname:
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filenames:
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filenames:
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filenames: intel_vvp_core_io.h
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filenames: src_hdl
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filenames: altera_up_avalon_video_dma_controller.c
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dirname:
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filenames: src_hdl
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dirname:
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filenames: src_hdl
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filenames: mon_inc.tcl/mon_reg_map.tcl
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filenames: alt_vip_common_mult_add_nodsp.sv
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filenames: altera_ldpc_nasa_enc.sv/altera_ldpc_nasa_enc_mat.sv
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filenames: src_hdl
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filenames: alt_vip_warp_line_store.sv
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dirname:
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filenames: counter_gen.sv/driver_top.sv/reg_delay.sv/reset_sync.v
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filenames: tb_run.sh/tb_top.ucli.txt/vcs_wave.tcl
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filenames: src_hdl
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dirname:
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filenames: gen_inc.tcl/gen_reg_map.tcl
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dirname:
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filetypes: ffffff
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filenames:
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filenames: src_hdl
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dirname:
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filenames: cm_rule_basic_enhanced_pcs.tcl/cm_rule_basic_enhanced_pcs_tb.tcl
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dirname:
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filenames: pio_reg_registers.h/qdma_regs_2_registers.h
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dirname:
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filenames: alt_vip_tpg_alg_core.sv
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dirname:
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filenames: intel_vvp_scaler_coeff_handler.sv
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dirname:
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filenames: intel_vvp_message_to_vvp_conv.ocp/intel_vvp_message_to_vvp_conv.sv
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dirname:
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filetypes: ffffff
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filenames:
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filenames: 40g/altera/common/main.tcl/reg_test.tcl
filetypes: dddff
dirname:
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filenames: intel_vvp_snoop_core.sv
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dirname:
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filetypes: ffffff
dirname:
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filenames:
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filetypes: ffff
dirname:
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filenames:
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filenames: alt_vip_warp_addr_gen.sv/alt_vip_warp_multiply.sv
filetypes: ff
dirname:
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filetypes: fffffff
dirname:
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filenames:
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filenames: altera_eth_default_slave.v
filetypes: f
dirname:
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filenames: intel_vvp_pkt_duplicator.sv
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dirname:
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filetypes: ffffffffffff
dirname:
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filenames:
  intel_qdma_desc_wb_tlp_gen.sv/intel_qdma_msix_controller.sv/intel_qdma_msix_irq_arbiter.sv/intel_qdma_msix_irq_processor.sv/intel_qdma_msix_package.sv/intel_qdma_msix_pba_table.sv/intel_qdma_msix_sdp_ram.sv/intel_qdma_msix_set_clr_rd.sv/intel_qdma_msix_st_arbiter.sv/intel_qdma_msix_tdp_ram.sv/intel_qdma_msix_tlp_arbiter.sv/intel_qdma_msix_tlp_gen.sv


filenames: alt_vip_vfb_sync_ctrl.sv
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filenames: demo_control/sliv_ip_toolkit_agilex/sliv_ip_toolkit_s10/system_console/top
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dirname:
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filetypes: dfffdddd
dirname:
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filenames:
  aldec/altera_eth_tse_pcs.sdc/altera_eth_tse_pcs.v/altera_eth_tse_pcs_hw.tcl/cadence/intelfpga/mentor/synopsys


filenames: default_test_params_pkg.sv.terp/ed_sim
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filenames: altera_oct.sv/altera_oct_um_fsm.sv
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dirname:
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filenames: csr_scripts/design_example_components/source
filetypes: ddd
dirname:
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filetypes: dfffffdddd
dirname:
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filenames:
  aldec/auk_vit_par_ber_atl.vhd/auk_vit_par_bmp_atl.vhd/auk_vit_par_top_atl.ocp/auk_vit_par_top_atl.vhd/auk_vit_par_trb_atl.vhd/cadence/intelfpga/mentor/synopsys


filetypes: fffffff
dirname:
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filenames:
  intel_vab_binary_to_gray.sv/intel_vab_clock_crosser.sv/intel_vab_counter_clock_crosser.sv/intel_vab_flop_primitive.sv/intel_vab_gray_to_binary.sv/intel_vab_ring_clock_crosser.sv/intel_vab_synchronizer_flop.sv


filenames: example_design.sv/ilk_pkt_checker.sv/ilk_pkt_gen.sv/top_tb.txt/vlog.do
filetypes: fffff
dirname:
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filenames: rtl
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dirname:
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filenames: intel_vvp_guard_bands_scheduler.sv
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dirname:
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filenames: alt_aeu_100_efc_top.v/alt_aeu_100_sfc_top.v
filetypes: ff
dirname:
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filenames: alt_e40_block_distributor.v/alt_e40_pcs.v/alt_e40_pcs_rx.v/alt_e40_pcs_tx.v
filetypes: ffff
dirname:
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filetypes: fffffffffffffffffffffffffff
dirname:
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filenames:
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filenames: inc/src
filetypes: dd
dirname:
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filetypes: fffffffffffffffffffffffffff
dirname:
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filenames:
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filenames: c3_reconfig.c/c3_reconfig.h/flow.c/main.c
filetypes: ffff
dirname:
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dirname: /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/alt_xcvr/alt_xcvr_ip_lib
filetypes: dddddddddddddddddddddddddddddddddddddddddddddd
filenames:
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filenames: altera_rs_ser_search.sv
filetypes: f
dirname:
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filenames: altera_iopll_reconfig_core.v/altera_iopll_reconfig_mif_reader.v/altera_pll_reconfig_top.v
filetypes: fff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/altera_pll_reconfig/intelfpga


filetypes: ffffffffffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/dsp/intel_fpga_polar_5g/src/aldec/rtl/enc

filenames:
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filenames: altera_avalon_interrupt_source_vhdl.vhd/altera_avalon_interrupt_source_vhdl_pkg.vhd
filetypes: ff
dirname:
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filenames: alt_vip_common_round_sat.sv
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filenames: aldec/cadence/intel_vvp_cpp_adapter_hw.tcl/intelfpga/mentor/src_hdl/synopsys
filetypes: ddfdddd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/vvp/component_library/tcl_components/utility/intel_vvp_cpp_adapter


filenames: alt_e40_tx_e4x10_base.v
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/alt_eth_40g_100g/40gbe/rtl_src/phy/mentor/pma_siv/alt_e40_tx_e4x10


filenames: intel_vvp_ro_reg_servicer.sv
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/vvp/component_library/tcl_components/utility/intel_vvp_ro_reg_servicer/cadence/src_hdl


filetypes: ffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/ethernet/alt_em10g32/example_design/LL10G_10G_USXGMII/rtl/pll_fpll

filenames:
[cell repeats an earlier one in this file: 103 characters]


filetypes: ffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/vvp/component_library/hdl_modules/pip_conv/cadence

filenames:
  intel_vvp_pack_hard.sv/intel_vvp_pack_simple.sv/intel_vvp_pip_bunch.sv/intel_vvp_pip_merge.sv/intel_vvp_unpack_hard.sv/intel_vvp_unpack_simple.sv


filenames: aldec/altera_eth_mdio.v/altera_eth_mdio_hw.tcl/cadence/intelfpga/mentor/synopsys
filetypes: dffdddd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/ethernet/ethernet_ucore/altera_eth_mdio


filenames: src_hdl
filetypes: d
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/vip/ip_library/common_hdl/modules/alt_vip_common_round_sat


filenames: intel_vvp_protocol_conv_hw.tcl/sw
filetypes: fd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/vvp/component_library/tcl_cores/intel_vvp_protocol_conv


filetypes: fffffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/vvp/component_library/tcl_components/imported/3d_lut/intel_vvp_3d_lut_core/intelfpga/src_hdl

filenames:
  intel_vvp_3d_lut_addr_decode.sv/intel_vvp_3d_lut_avlmm_if.sv/intel_vvp_3d_lut_axis_shim.sv/intel_vvp_3d_lut_config.sv/intel_vvp_3d_lut_cpu_bridge.sv/intel_vvp_3d_lut_ctrl_if.sv/intel_vvp_3d_lut_dsp.sv/intel_vvp_3d_lut_interp_tetra.sv/intel_vvp_3d_lut_ram_proc_if.sv/intel_vvp_3d_lut_switch.sv/intel_vvp_3d_lut_top.sv


filenames: intel_pcie_ReadyDelay.sv
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/intel_pcie/soft_switch/sep/rtl/intelfpga/common/avmmReady


filetypes: dfffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffdddd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/alt_interlaken/alt_ntrlkn_8l_3g

filenames:
  aldec/alt_ntrlkn_8l_3g_align_dcf.v/alt_ntrlkn_8l_3g_align_fifo.v/alt_ntrlkn_8l_3g_alignment_pipe.v/alt_ntrlkn_8l_3g_arbiter.v/alt_ntrlkn_8l_3g_avalon_to_ilk_adapter_2.v/alt_ntrlkn_8l_3g_buffer_1_to_2.v/alt_ntrlkn_8l_3g_buffer_2_to_1.v/alt_ntrlkn_8l_3g_buffered_read_scheduler_2.v/alt_ntrlkn_8l_3g_channel_fifo.v/alt_ntrlkn_8l_3g_crc24_dat64.v/alt_ntrlkn_8l_3g_crc24_dat64_factor.v/alt_ntrlkn_8l_3g_crc24_dat64_flat.v/alt_ntrlkn_8l_3g_crc24_dat64_only_flat.v/alt_ntrlkn_8l_3g_crc24_multiple_upto2.v/alt_ntrlkn_8l_3g_crc24_multiple_upto3.v/alt_ntrlkn_8l_3g_crc24_zer64_flat.v/alt_ntrlkn_8l_3g_crc24_zer64x2_flat.v/alt_ntrlkn_8l_3g_crc24_zer64x3_flat.v/alt_ntrlkn_8l_3g_crc32c_dat64.v/alt_ntrlkn_8l_3g_crc32c_dat64_factor.v/alt_ntrlkn_8l_3g_crc32c_dat64_flat.v/alt_ntrlkn_8l_3g_crc32c_dat64_only.v/alt_ntrlkn_8l_3g_crc32c_dat64_only_factor.v/alt_ntrlkn_8l_3g_crc32c_dat64_only_flat.v/alt_ntrlkn_8l_3g_crc32c_zer64.v/alt_ntrlkn_8l_3g_crc32c_zer64_factor.v/alt_ntrlkn_8l_3g_crc32c_zer64_flat.v/alt_ntrlkn_8l_3g_dec_67_64.v/alt_ntrlkn_8l_3g_enc_64_67.v/alt_ntrlkn_8l_3g_fifo_36_to_72.v/alt_ntrlkn_8l_3g_fifo_72_to_36.v/alt_ntrlkn_8l_3g_frame_sync_control.v/alt_ntrlkn_8l_3g_gearbox_20_67.v/alt_ntrlkn_8l_3g_gearbox_67_20.v/alt_ntrlkn_8l_3g_hw.tcl/alt_ntrlkn_8l_3g_ilk_to_avalon_adapter_2.v/alt_ntrlkn_8l_3g_lal_cfifo.v/alt_ntrlkn_8l_3g_lal_dcfifo.v/alt_ntrlkn_8l_3g_lal_dfifo_auto.v/alt_ntrlkn_8l_3g_lane_alignment.v/alt_ntrlkn_8l_3g_lane_alignment_nav.v/alt_ntrlkn_8l_3g_lane_alignment_ram.v/alt_ntrlkn_8l_3g_lane_rx.v/alt_ntrlkn_8l_3g_lane_rx_crc.v/alt_ntrlkn_8l_3g_lane_status_monitor.v/alt_ntrlkn_8l_3g_lane_tx.v/alt_ntrlkn_8l_3g_lane_tx_crc.v/alt_ntrlkn_8l_3g_packet_annotate.v/alt_ntrlkn_8l_3g_packet_regroup_2.v/alt_ntrlkn_8l_3g_pipelined_any_flag.v/alt_ntrlkn_8l_3g_ram_navigate.v/alt_ntrlkn_8l_3g_read_calendar_2.v/alt_ntrlkn_8l_3g_read_calendar_single_page_2.v/alt_ntrlkn_8l_3g_read_scheduler_2.v/alt_ntrlkn_8l_3g_ready_skid.v/alt_ntrlkn_8l_3g_regroup_2.v/alt_ntrlkn_8l_3g_routing_pipe.v/alt_ntrlkn_8l_3g_rx_8lane.v/alt_ntrlkn_8l_3g_rx_buffer_fifo_2.v/alt_ntrlkn_8l_3g_rx_channel_filter_2.v/alt_ntrlkn_8l_3g_rx_crc24_check_2.v/alt_ntrlkn_8l_3g_rx_datapath_8lane.v/alt_ntrlkn_8l_3g_rx_stripe_adapter.v/alt_ntrlkn_8l_3g_scrambler_lfsr.v/alt_ntrlkn_8l_3g_sim_packet_client.v/alt_ntrlkn_8l_3g_six_three_comp.v/alt_ntrlkn_8l_3g_sum_of_3bit_pair.v/alt_ntrlkn_8l_3g_synchronizer.v/alt_ntrlkn_8l_3g_ternary_add.v/alt_ntrlkn_8l_3g_twelve_four_comp.v/alt_ntrlkn_8l_3g_tx_2channel_arbiter.v/alt_ntrlkn_8l_3g_tx_4channel_arbiter.v/alt_ntrlkn_8l_3g_tx_8lane.v/alt_ntrlkn_8l_3g_tx_buffer_fifo_8word.v/alt_ntrlkn_8l_3g_tx_buffer_fifo_nav.v/alt_ntrlkn_8l_3g_tx_buffer_fifo_ram.v/alt_ntrlkn_8l_3g_tx_buffer_fifo_ram_loose.v/alt_ntrlkn_8l_3g_tx_control_insertion_2.v/alt_ntrlkn_8l_3g_tx_crc24_insertion_2.v/alt_ntrlkn_8l_3g_tx_datapath_8lane.v/alt_ntrlkn_8l_3g_tx_flow_adapter.v/alt_ntrlkn_8l_3g_tx_stripe_adapter.v/alt_ntrlkn_8l_3g_wide_word_ram.v/alt_ntrlkn_8l_3g_wide_word_ram_4.v/alt_ntrlkn_8l_3g_word_align_control.v/alt_ntrlkn_8l_3g_xcvr_8lane.v/alt_ntrlkn_8l_3g_xor6.v/cadence/intelfpga/mentor/synopsys


filenames: altera_oct_driver.sv
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/altera_oct/altera_oct_driver/mentor


filenames: j204c_rx_regmap.v
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/jesd204c_f/src/rx/cadence/rdf/csrgen_output


filenames: eth_ex_100g_a10.qpf/eth_ex_100g_a10.qsf/eth_ex_100g_a10.v
filetypes: fff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/ethernet/alt_eth_ultra/example_project/100g_a10


filenames: eth_ex_40g_a10.qpf/eth_ex_40g_a10.qsf/eth_ex_40g_a10.v
filetypes: fff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/ethernet/alt_eth_ultra/example_project/40g_a10


filenames: parameter.tcl
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/ethernet/alt_em10g32/example_design/LL10G_1G_10G_LINESIDE_1588v2/hwtesting/system_console/test_parameter


filenames: src_hdl
filetypes: d
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/vip/ip_library/common_hdl/modules/alt_vip_common_frame_counter


filetypes: dfffdddd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/ethernet/tse_ucores/altera_eth_tse_pcs_2xtbi

filenames:
  aldec/altera_eth_tse_pcs_2xtbi.sdc/altera_eth_tse_pcs_2xtbi.v/altera_eth_tse_pcs_2xtbi_hw.tcl/cadence/intelfpga/mentor/synopsys


filenames: alt_aeu_100_pfc_top.v
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/ethernet/alt_eth_ultra/100g/rtl/pfc/top


filenames: src_hdl
filetypes: d
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/vvp/component_library/tcl_components/utility/intel_vvp_slave_data_split/synopsys


filetypes: fffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/ethernet/alt_e50s10/50g/cadence/rtl/csr

filenames:
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filenames: altpciexpav_lite_app.v
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/altera_pcie/altera_pcie_av_hip_avmm/synopsys/avalon_lite


filetypes: fffffffffffffffffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/ethernet/alt_eth_ultra/40g_ptp/cadence

filenames:
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filetypes: fffffffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/altera_dp/src/aldec/displayport2p0/tx/txll/common/dp2p0_txll_lib/embedded_ram

filenames:
  dp2p0_txll_dc_2p_ram.v/dp2p0_txll_dc_2p_ram_cebe.v/dp2p0_txll_dc_2p_ram_mw.v/dp2p0_txll_dc_2p_ram_mw_cebe.v/dp2p0_txll_dcfifo.v/dp2p0_txll_dcfifo_mw.v/dp2p0_txll_sc_1p_ram.v/dp2p0_txll_sc_1p_ram_cebe.v/dp2p0_txll_sc_2p_ram.v/dp2p0_txll_sc_2p_ram_cebe.v/dp2p0_txll_sc_true_2p_ram.v/dp2p0_txll_sc_true_2p_ram_cebe.v/dp2p0_txll_scfifo.v


filenames: altera_eth_frame_status_merger.v
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/ethernet/ethernet_ucore/altera_eth_frame_status_merger/mentor


filenames: rtl
filetypes: d
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/subsystems/mem_ss/ip_reset_sim_source/aldec


filenames: intel_vvp_pkt_demux.sv
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/vvp/component_library/tcl_components/utility/intel_vvp_pkt_demux/src_hdl


filenames: bitec_hdmi_tx_audio.v/bitec_hdmi_tx_audio_mux.v
filetypes: ff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/altera_hdmi/src/hdmi_2.0/tx/synopsys/audio


filenames: alt_e40_adapter.v/alt_e40_wide_l2if_rx_mux.v/alt_e40_wide_l2if_tx.v
filetypes: fff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/ethernet/alt_e40/40g/rtl/ast


filenames: alt_vip_stream_cleaner_alg_core.ocp/alt_vip_stream_cleaner_alg_core.sv
filetypes: ff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/vip/ip_library/component_ip/processing/alt_vip_stream_cleaner_alg_core/src_hdl


filenames: soft_lckppm_det.v
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/sdi_ii/soft_lockppm_det/aldec


filenames: src_hdl
filetypes: d
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/vip/ip_library/common_hdl/cadence/modules/alt_vip_common_to_binary


filenames: src_hdl
filetypes: d
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/vip/ip_library/component_ip/utility/alt_vip_packet_demux/aldec


filenames: gdr_adapters/soft_logics
filetypes: dd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/intel_pcie/ftile/common/rtl/intelfpga


filenames: src_hdl
filetypes: d
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/vvp/component_library/tcl_components/algorithmic_components/intel_vvp_tpg_sdi_algo_comp/synopsys


filetypes: fffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/ethernet/alt_em10g32/example_design/LL10G_1G_2_5G_10G_1588v2/rtl/reconfig

filenames:
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filenames: inc
filetypes: d
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/vvp/component_library/tcl_cores/intel_vvp_warp/sw/intel_vvp_warp_driver/HAL


filenames: alt_vip_common_event_packet_encode.sv
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/vip/ip_library/common_hdl/synopsys/modules/alt_vip_common_event_packet_encode/src_hdl


filenames: alt_vip_common_sync.v
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/vip/ip_library/common_hdl/synopsys/modules/alt_vip_common_sync/src_hdl


filenames: common/fm/s10
filetypes: ddd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/ethernet/alt_ehipc2/mentor/rtl/alt_ehipc2_lib/hslx


filenames: intel_vab_pipelined_mux.sv
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/video_axi_bridges/component_library/hdl_modules/pixel_shift/mentor


filetypes: ffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/vvp/component_library/tcl_components/schedulers/intel_vvp_vert_scaler_scheduler/aldec/src_hdl

filenames:
  intel_vvp_vert_scaler_scheduler.sv/intel_vvp_vert_scaler_scheduler_ctrl_out.sv/intel_vvp_vert_scaler_scheduler_ext_ctrl.sv/intel_vvp_vert_scaler_scheduler_init.sv/intel_vvp_vert_scaler_scheduler_int_ctrl.sv/intel_vvp_vert_scaler_scheduler_main.sv


filenames: intel_fpga_iv_tqor_monitor.sv.terp/intel_fpga_iv_tqor_monitor_hw.tcl
filetypes: ff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/iv/intel_fpga_iv_tqor_monitor


filetypes: ffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/altera_hdmi/src/ipxact/tx/hdmi_tx_registers

filenames:
  Vendor_Library_hdmi_tx_registers_2014.ipxact/hdmi_tx_reg.csv/hdmi_tx_reg.v/hdmi_tx_reg_cmsis_component_CMSIS_1_1_draft.svd


filenames: intel_pcie_adapter_rx_if.sv/intel_pcie_adapter_stos.sv/intel_pcie_adapter_tx_if.sv
filetypes: fff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/intel_pcie/ptile/common/rtl_legacy/whr_adapters/adapter_single_segment


filetypes: ffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/altera_uflex_interlaken/uflex_ilk_pcs/mentor

filenames:
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filenames: axi_ocram_hw.tcl/gen_hps_perifs_tcl.sh/timer_hw.tcl
filetypes: fff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/altera_hps/s10/device_tree_generation


filenames: altera_emif_ddrt_model.sv/altera_emif_ddrt_model_base.sv/altera_emif_simbus.sv
filetypes: fff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/emif/ip_mem_model/ip_core_ddrt/synopsys/rtl


filenames: testbench/tse_1588.qsys/tse_1588_top.sdc/tse_1588_top.v
filetypes: dfff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/ethernet/altera_eth_tse_design_example/tse_ieee1588_a10


filenames: altera_eth_tse_ftile_phyip_terminator.v
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/ethernet/tse_ucores/altera_eth_tse_ftile_phyip_terminator/aldec


filetypes: fffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/alt_interlaken_hp/testbench/example_design_50g_a10

filenames:
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filetypes: ffffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/vip/ip_library/component_ip/processing/alt_vip_scaler_alg_core/cadence/src_hdl

filenames:
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filenames: altera_up_avalon_video_pixel_buffer_dma.v
filetypes: f
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/university_program/audio_video/video/altera_up_avalon_video_pixel_buffer_dma/hdl


filenames: src_hdl
filetypes: d
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/vip/ip_library/common_hdl/mentor/modules/alt_vip_common_slave_interface


filetypes: ffffffffffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/alt_xcvr/altera_xcvr_10gbase_kr/sv_soft_10gbaser/aldec/sv_soft_pcs

filenames:
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filenames: rnr_pcie_ehp_pack/rnr_pcie_ehp_tx_deallocate_ctr.sv/rnr_pcie_ehp_unpack/rnr_pcie_ehp_wrapper.sv
filetypes: dfdf
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/intel_rtile/pcie/common/rtl/spyglass/soft_wrapper/rnr_pcie_ehp


filetypes: ffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/intel_pcie/avmm_bridge_512_ed/intel_pcie_mem

filenames:
[cell repeats an earlier one in this file: 100 characters]


filenames: address_decoder_top_traffic_controller_ch_6_7.v/altera_merlin_slave_translator_tch_6_7.sv
filetypes: ff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/ethernet/altera_eth_tse/example_project/common/hw/dec/ip/top/address_decoder_top_traffic_controller_ch_6_7


filenames: lib_obf/main_umts_dec.c/main_umts_enc.c
filetypes: dff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/dsp/altera_turbo/UMTS/src/c


filenames: tb_run.sh/xcelium_wave.tcl
filetypes: ff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/ethernet/alt_em10g32/example_design/LL10G_1G_10G_LINESIDE_1588v2/simulation/ed_sim/xcelium


filetypes: fffffffffff
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/vvp/component_library/tcl_components/imported/3d_lut/intel_vvp_3d_lut_core/synopsys/src_hdl

filenames:
  intel_vvp_3d_lut_addr_decode.sv/intel_vvp_3d_lut_avlmm_if.sv/intel_vvp_3d_lut_axis_shim.sv/intel_vvp_3d_lut_config.sv/intel_vvp_3d_lut_cpu_bridge.sv/intel_vvp_3d_lut_ctrl_if.sv/intel_vvp_3d_lut_dsp.sv/intel_vvp_3d_lut_interp_tetra.sv/intel_vvp_3d_lut_ram_proc_if.sv/intel_vvp_3d_lut_switch.sv/intel_vvp_3d_lut_top.sv


filetypes: fffffffffffffffffffffffd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/seriallite_iii/example/example_design/demo_control

filenames:
[cell repeats an earlier one in this file: 623 characters]


filenames: basic_avl_tb_top.sv.terp/mentor/s10/synopsys/xcelium
filetypes: fdddd
dirname:
  /opt/intel/oneapi/intelfpgadpcpp/2022.2.0/QuartusPrimePro/21.4/ip/altera/dynamic_reconfiguration/etile_dynamic_reconfiguration/example_design/ETH25G_PTP_RSFEC_CPRI/example_testbench


